Threshold voltage instability in silicon carbide power MOSFET

The present research aims to understand the influence of the charge trapping rate in Silicon Carbide (SiC) metal-oxide semiconductor-field-e↵ect-transistors (MOSFETs) which nowadays have special interest for high power applications. It’s very important the study of the reliability of this new generation of high power devices according to the applications such as solar inverters..La presente investigación tiene como objetivo comprender la influencia de la tasa de captura de carga en transistores de efecto de campo metal-óxido-semiconductor (MOSFET) de carburo de silicio (SiC), que en la actualidad tienen un interés especial para aplicaciones de alta potencia. Es muy importante el estudio de la confiabilidad de esta nueva generación de dispositivos de alta potencia de acuerdo con las aplicaciones tales como inversores solares..

Impact of BTI induced threshold voltage shifts in shoot-through currents from crosstalk in SiC MOSFETs

In this paper a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-ON to characterize the impact of Bias Temperature Instability (BTI) induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge de-trapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal and polarity of the stress have been studied for a set of commercially available SiC MOSFETs

Optimisation of the gate voltage in SiC MOSFETS: efficiency vs reliability

This paper presents a comprehensive study of the impact of the gate voltage on the switching and ON-state performance of SiC MOSFETs. It is well known that the gate oxide in SiC MOSFETs is not as reliable as that in silicon MOSFETs due to increased fixed oxide and interface traps. Numerous studies have shown reduced performance on time-dependent dielectric breakdown (TDDB) and oxide robustness in SiC MOSFETs compared to silicon devices. On the one hand, a high ON-state gate-source voltage VGS is required for proper channel inversion, low ON-state loss and fast switching while on the other hand, a lower ON-state VGS reduces the electrical stress on the gate oxide and improves long term reliability. Understanding the implications of the selected gate voltage on the operation of the power device will be fundamental for achieving an optimal balance between electrical performance and gate oxide reliability. This paper shows that reducing the maximum gate driver supply voltage VGG only affects turn-ON losses while turn-OFF losses are independent of VGG. The experimental characterisation is complemented with electrothermal simulations to evaluate the impact of the gate voltage on the operation of a converter. The paper shows that reducing VGG by 10% causes an increase of 7.6 % in the device losses and 1.4 °C in junction temperature in simulated converter operation. Furthermore, if the switching speed is increased by means of reducing the gate resistance, the impact of the conduction losses can be compensated. These results are fundamental for balancing system efficiency and reliability in SiC MOSFETs

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Technology and reliability of normally-off GaN HEMTs with p-type gate

open4siopenMeneghini, Matteo*; Hilt, Oliver; Wuerfl, Joachim; Meneghesso, GaudenzioMeneghini, Matteo; Hilt, Oliver; Wuerfl, Joachim; Meneghesso, Gaudenzi

Technology and reliability of normally-off GaN HEMTs with p-type gate

GaN-based transistors with p-GaN gate are commonly accepted as promising devices for application in power converters, thanks to the positive and stable threshold voltage, the low on-resistance and the high breakdown field. This paper reviews the most recent results on the technology and reliability of these devices by presenting original data. The first part of the paper describes the technological issues related to the development of a p-GaN gate, and the most promising solutions for minimizing the gate leakage current. In the second part of the paper, we describe the most relevant mechanisms that limit the dynamic performance and the reliability of GaN-based normally-off transistors. More specifically, we discuss the following aspects: (i) the trapping effects specific for the p-GaN gate; (ii) the time-dependent breakdown of the p-GaN gate during positive gate stress and the related physics of failure; (iii) the stability of the electrical parameters during operation at high drain voltages. The results presented within this paper provide information on the current status of the performance and reliability of GaN-based E-mode transistors, and on the related technological issues

Reliable time exponents for long term prediction of negative bias temperature instability by extrapolation

To predict the negative bias temperature instability (NBTI) towards the end of pMOSFETs’ 10 years lifetime, power-law based extrapolation is the industrial standard method. The prediction accuracy crucially depends on the accuracy of time exponents, n. The n reported by early work spreads in a wide range and varies with measurement conditions, which can lead to unacceptable errors when extrapolated to 10 years. The objective of this work is to find how to make the n extraction independent of measurement conditions. After removing the contribution from as-grown hole traps (AHT), a new method is proposed to capture the generated defects (GD) in their entirety. The n extracted by this method is around 0.2 and insensitive to measurement conditions for the four fabrication processes we tested. The model based on this method is verified by comparing its prediction with measurements. Under AC operation, the model predicts that GD can contribute to ~90% of NBTI at 10 years