Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability

Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier\u27s voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses

Characterization of negative bias temperature instability and lifetime prediction for pMOSFETs

In order to achieve high speed and packing density, the size of the transistor has shrunk aggressively. The gate dielectric, as the most critical component in the transistor, is undergoing rapid and substantial changes with the adoption of ultra-thin plasma nitrided oxide and more recently high-k dielectrics. As the nitrogen concentration in silicon oxynitrides (SiON) increases, the negative bias temperature instability (NBTI) rises and becomes a limiting factor for device lifetime. The NBTI can recover significantly during typical measurement time when using conventional instruments. To suppress this recovery, several fast techniques have been developed, including ultra-fast pulse Id-Vgtechnique and the On-The-Fly technique. These techniques, however, give different threshold voltage degradation (~VI) after the same stress. The interpretation of this difference is still controversial. The objective of chapter 3 is to bridge the gap between the ~Vt extracted from these techniques. Degradation and recovery during measurement, measurement and truncation errors, and evaluation of transconductance are examined. After taking these factors into account, the gap in llVt still cannot be filled. The effect of the sensing Vg on l::,.Vits considered and it is found that 111VtinI creases with sensing IVgl.The popular assumption of t:.Vt being independent of sensing Vg is invalid, thereafter. After taking both the effect of sensing Vg and recovery into account, the gap in llVt is successfully bridged. The difference between the effect of sensing Vg and recovery is explored, and the results show that they are two different phenomena. The recovery suppression and the sensing Vg effect challenge the applicability of the traditional lifetime prediction technique. In a large circuit with roughly 106 MOSFETs, there will always be some of them under the worst case condition, namely constant stress without recovery. The failure of one of these MOSFETs can lead to the malfunction of the whole circuit. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can be applied. In chapter 4, the worst case lifetime prediction is investigated. It is found that the prediction based on the Vg acceleration results in substantial errors. To predict the worst-case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects and it no longer follows a simple power law. Based on the new kinetics, a single test prediction method is proposed and its safety margin is estimated to be 50%. Mobility reduction is another important issue when oxide thickness becomes thinner. It is reported that when the gate SiON becomes thinner than 2 nm or the interfacial layer in high-k stack is thinner than 2.5 nm, carrier mobility reduces. Agreement has not yet been reached on the level of reduction, or on the underlying mechanism. Remote charge scattering (ReS) has been proposed to be responsible for this mobility reduction. However, one weakness of earlier work is that different samples were used when experimentally studying the Res and this introduces uncertainties. For example, a reduction in oxide thickness does not only bring the gate closer to the substrate, but also modulates other factors such as surface roughness. In chapter 5, the importance of ReS is assessed by varying charge in the same device through either processing or electron trapping, to remove the uncertainties from using different devices. It is found that by increasing charge density at 0.56 - 1 nm from the substrate interface to the order of 1020 ern", both electron and hole mobility change little

TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Development of characterization techniques for negative bias temperature instabilities

The requirements for ever faster circuits and higher packing density have driven the continuous downscaling of the transistor sizes in the last 50 years or so. This leads to higher electrical field and operation temperature and, in turn, accelerates the degradation. One of the most serious reliability issues for the current CMOS technology is the negative bias temperature instability (NETI). This project will focus on investigating the NBTI and the positive charges responsible for it. Modem MOSFETs use gate dielectrics in the nanometer range and the degradation will recover rapidly. To suppress the recovery, high speed characterization technique is needed. In this project the measurement speed has been improved from Sus to 200 ns for Id-Vg measurements and 800ns for C- V measurement. As a Hf-dielectric/SiON stack is replacing SiON as the gate dielectric, the task is to identify which layer of the stack dominates positive charging (PC). A main achievement in this project is the finding that PCs are dominated by the interfacial layer (IL) and they do not pile up at the HfSiON/(IL) interface. Evaluating the conventional threshold voltage shift measured by extrapolating transfer characteristics, ? Vth( ex), underestimates the NBTI-induced degradation of drain current, ?ld. In this project we proposed the effective threshold voltage shift, ? Veff, in order to evaluate the devices degradation correctly. The next task was to develop a lifetime prediction method, based on ?Veff. To predict the worst-case lifetime which is recovery free, a model for NBTI kinetics under operation gate bias was developed. This kinetics includes contributions from both as-grown and generated defects and it no longer follows a simple power law. Based on the new kinetics, a single test prediction method was proposed and its safety margin is estimated to be 50%. A fast single pulse charge pumping (SPCP) technique was developed in this project, reducing the measurement time to microseconds. By exploring the differences in the transient currents corresponding to the two edges of the gate pulse, the net charges pumped into devices can be obtained and their saturation level is used to evaluate interface states. For the first time, SPCP allows the recovery of interface states to be monitored with a time resolution in microseconds. The results show that the recovery of stress-induced interface states is substantial within 100?s, which would be missed if conventional charge pumping were used

Characterization of high-k layers as the gate dielectric for MOSFETs

As the gate oxide thickness of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is continuously scaled down with lateral device dimensions, the gate leakage current during operation increases exponentially. This increase in leakage current raises concerns regarding power consumption and device reliability. Alternative dielectrics with higher dielectric constant (high-k) than that of Si02 have been searched. High-k layers allow the use of physically thicker gate dielectrics, so that the gate leakage current is controlled. The intensive world-wide research has identified the Hf-dielectric as the lead candidate for future CMOS technologies. However, the commercial application of Hf-dielectrics as the gate oxide has been held back by a number of issues, including process integration, low carrier mobility, and high instability. This project focuses on characterizing the defect responsible for the instability of Hf-dielectrics. The thesis consists of six chapters. After an introduction in Chapter 1, the characterization techniques used are described in Chapter 2. Two main contributions are: setting up the pulse transfer characteristic technique and developing a newly improved charge pumping technique called Variable T charged is charge Pumping (VT2CP). The research results are presented in Chapters 3,4 and 5. Chapter 3 characterizes a s-grown electron traps in HfO2/SiO2s tacks. The issues addressed include the impact of measurement technique on electron trapping, contribution of different current components to trapping, trap location, and the capture cross section and trapping kinetics. It is shown that the use of pulse transfer characteristic technique is essential for measuring electron trapping, since the traditional quasi-dc transfer characteristic is too IV ABSTRACT slow and the loss of charges is significant. The trap assisted tunneling and the thermally enhanced conduction contributes little to trapping. The trapping does not pile up at the interfaces and the region near to one or both ends of Hf02 has little trapping, when compared with the trapping in the bulk. To evaluate the electron fluency through the gate stack, efforts are made to estimate the trapping-induced transient gate current through simulation. This allows the determination of two capture cross sections: one in the order of 10-14cma2n d the other in the order of 10-16cm2. Chapter 4 concentrates on the characterization of generated electron traps and the time dependent dielectric breakdown (TDDB). Amplitude charge pumping and frequency sweep charge pumping are used to investigate the impact of gate electrodes and channel length on charging and discharging of the bulk defects. As channel length increases,it is found that bulk trapping increases and TDDB time shortens. Efforts are made to show that there is a quantitative correlation between the trapping and TDDB data. The newly improved VTZCP is used to separate trapping in the interfacial Si02 from that in Hf02. The results show that new traps are generated in both layers and the generation follows a power law with similar power factors. Investigation is also carried out to assess the dependence of trap generation on process and deposition conditions. Finally, it is found that Hf-dielectric with metal gate always suffers hard-breakdown. In Chapter 5, attention is turned to positive charging in Hf-dielectric. It is shown that the use of metal gate enhances the positive charging, when stressed under a positive gate bias. This is explained by assuming that there is a large number of hydrogenous species within the metal gate or at its interface with gate dielectric. Two types of threshold voltage instabilities have been identified for pMOSFETs. The first one results in a loop in the transfer characteristics when a pulse is applied to the gate. The second one is caused by the generation of new positive charge. Both are enhanced by V ABSTRACT nitridation. For sub-2nm Hf-dielectric, the threshold voltage instability of pMOSFETs can be more severe than that of nMOSFETs and it can be a limiting factor for the operation voltage. Finally, the project is summarized in Chapter 6 and the future work is discussed

Mechanism of dynamic bias temperature instability in p- and nMOSFETs: The effect of pulse waveform

The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current-voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction-diffusion (R-D) model and with an assumption that additional interface traps (N*it) are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the SiO2/Si interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si-H bonds at the beginning of the stressing phase in each cycle. Hence, N*it depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R-D model

Probing technique for energy distribution of positive charges in gate dielectrics and its application to lifetime prediction

The continuous reduction of the dimensions of CMOS devices has increased the negative bias temperature instability (NBTI) of pMOSFETs to such a level that it is limiting their lifetime. This increase of NBTI is caused mainly by three factors: an increase of nitrogen concentration in gate dielectric, a higher operation electrical field, and a higher temperature. Despite of many years’ research work, there are questions on the correctness of the NBTI lifetime predicted through voltage acceleration and extrapolation. The conventional lifetime prediction technique measures the degradation slowly and it typically takes 10 ms or longer to record one threshold voltage shift. It has been reported that NBTI can recover substantially in this time and the degradation is underestimated. To minimize the recovery, ultra-fast technique has been developed and the measurement time has been reduced to the order of microseconds. Once the recovery is suppressed, however, the degradation no longer follows a power law and there is no industry-wide accepted method for lifetime prediction. The objective of this project is to overcome this challenge and to develop a reliable NBTI lifetime prediction technique after freezing the recovery. To achieve this objective, it is essential to have an in-depth knowledge on the defects responsible for the recovery. It has been generally accepted that the NBTI recovery is dominated by the discharge of trapped holes. For the thin dielectric (e.g. < 3 nm) used by current industry, all hole traps are within direct tunnelling distance from the substrate and their discharging is mainly controlled by their energy levels against the Fermi level at the substrate interface. As a result, it is crucial to have the energy distribution of positive charges (PC) in the gate dielectric, but there is no technique available for probing this energy profile. A major achievement of this project is to develop a new technique that can probe the energy distribution of PCs both within and beyond the silicon energy gap. After charging up the hole traps, they are allowed to discharge progressively by changing the gate bias, Vg, in the positive direction in steps. This allows the Fermi level at the interface to be swept from a level below the valence band edge to a level above the conduction band edge, giving the required energy profile. Results show that PCs can vary by one order of magnitude with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps which are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence band edge are from the created defects. The PCs within bandgap saturate for either longer stress time or higher stress temperature. In contrast, the PCs above conduction band edge, namely the anti-neutralization positive charges, do not saturate and their generation is clearly thermally accelerated. This energy profile technique is applicable to both SiON and high-k/SiON stack. It is found that both of them have a high level of as-grown hole traps below the valence band edge and their main difference is that there is a clear peak in the energy density near to the conduction band edge for the High-k/SiON stack, but not for the SiON. Based on this newly developed energy profile technique and the improved understanding, a new lifetime prediction technique has been proposed. The principle used is that a defect must be chargeable at an operation voltage, if it is to be included in the lifetime prediction. At the stress voltage, some as-grown hole traps further below Ev are charged, but they are neutral under an operation bias and must be excluded in the lifetime prediction. The new technique allows quantitative determination of the correct level of as-grown hole trapping to be included in the lifetime prediction. A main advantage of the proposed technique is that the contribution of as-grown hole traps is experimentally measured, avoiding the use of trap-filling models and the associated fitting parameters. The successful separation of as-grown hole trapping from the total degradation allows the extraction of generated defects and restores the power-law kinetics. Based on this new lifetime prediction technique, it is concluded that the maximum operation voltage for a 10 years lifetime is substantially overestimated by the conventional prediction technique. This new lifetime prediction technique has been accepted for presentation at the 2013 International Electron Devices Meeting (IEDM)

Threshold voltage instabilities in MOS transistors with advanced gate dielectrics

Ph.DDOCTOR OF PHILOSOPH

DEFECTS AND LIFETIME PREDICTION OF GERMANIUM MOSFETS

To continue improving device speed, much effort has been made to replace Si by high mobility semiconductors. Ge is considered as a strong candidate for pMOSFETs due to the high hole mobility. Two approaches have been demonstrated: high-k/Si-cap/Ge and high-k/GeO2/Ge. Negative Bias Temperature Instability (NBTI) is still one of the main reliability issues, limiting the device lifetime. In this project, it is found that the conventional lifetime prediction method developed for Si is inapplicable to Ge devicesand defect properties in Ge and Si MOSFETs are different.The threshold voltage degradation in Ge can be nearly 100% recovered under a much lower temperature than that in Si devices. The defect losses observed in Si devices were absent in Ge/GeO2/Al2O3. The generation of interface states is insignificant and the positive charges in GeO2/Al2O3 on Ge dominate the NBTI. These positive charges do not follow the same model as those in SiON/Si and an energy-alternating model has been proposed: there are a spread of energy levels of neutral hole traps below Ev andthey lift up after charging, and return below Ev after neutralization.The energy distribution of positive charges in the Al2O3/GeO2/Ge gate stack was studied by the Discharge-based Multi-pulse (DMP) Technique. The different stress-time dependence of defects below Ev and around Ec indicates that they originate from different defects. Quantization effect, Fermi level pinning, and discharge voltage step were considered. The defect differences in terms of the energy level were investigated by using the DMP technique and the energy alternating model is verified by the defect energy distribution.Based on the understanding of different defect behavior, a new NBTI lifetime prediction method was developed for Ge MOSFETs. Energy alternating defects were separated from as-grown hole traps (AHT), which enables to restore the power law for NBTI kinetics with a constant power exponent. The newly developed Ge method was applicable for NBTI lifetime prediction of the state-of-the-art Si-cap/Ge and GeO2/Ge MOSFETs. When compared with SiON/Si, the optimized Si-cap/Ge shows superior reliability, while GeO2/Ge is inferior and needs further optimization. Preliminary characterization was also carried out to investigate the impacts of energy levels and characteristic times of different defects on the frequency and duty factor dependence of AC NBTI degradation