Impedance matching and energy shunting control for nonpositive real structures

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1994.Includes bibliographical references (191-193).by Carl Blaurock.M.S

MAXIMA: A balloon-borne cosmic microwave background anisotropy experiment

Published versio

Investigation into digital audio equaliser systems and the effects of arithmetic and transform errors on performance

Merged with duplicate record 10026.1/2685 on 07.20.2017 by CS (TIS)Discrete-time audio equalisers introduce a variety of undesirable artefacts into audio mixing systems, namely, distortions caused by finite wordlength constraints, frequency response distortion due to coefficient calculation and signal disturbances that arise from real-time coefficient update. An understanding of these artefacts is important in the design of computationally affordable, good quality equalisers. A detailed investigation into these artefacts using various forms of arithmetic, filter frequency response, input excitation and sampling frequencies is described in this thesis. Novel coefficient calculation techniques, based on the matched z-transform (MZT) were developed to minimise filter response distortion and computation for on-line implementation. It was found that MZT-based filter responses can approximate more closely to s-plane filters, than BZTbased filters, with an affordable increase in computation load. Frequency response distortions and prewarping/correction schemes at higher sampling frequencies (96 and 192 kHz) were also assessed. An environment for emulating fractional quantisation in fixed and floating point arithmetic was developed. Various key filter topologies were emulated in fixed and floating point arithmetic using various input stimuli and frequency responses. The work provides detailed objective information and an understanding of the behaviour of key topologies in fixed and floating point arithmetic and the effects of input excitation and sampling frequency. Signal disturbance behaviour in key filter topologies during coefficient update was investigated through the implementation of various coefficient update scenarios. Input stimuli and specific frequency response changes that produce worst-case disturbances were identified, providing an analytical understanding of disturbance behaviour in various topologies. Existing parameter and coefficient interpolation algorithms were implemented and assessed under fihite wordlength arithmetic. The disturbance behaviour of various topologies at higher sampling frequencies was examined. The work contributes to the understanding of artefacts in audio equaliser implementation. The study of artefacts at the sampling frequencies of 48,96 and 192 kHz has implications in the assessment of equaliser performance at higher sampling frequencies.Allen & Heath Limite

Proceedings of the Workshop on Computational Aspects in the Control of Flexible Systems, part 2

The Control/Structures Integration Program, a survey of available software for control of flexible structures, computational efficiency and capability, modeling and parameter estimation, and control synthesis and optimization software are discussed

Acoustic noise suppression for helicopter communication systems

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Aeronautics and Astronautics, 1993.Includes bibliographical references (p. 143-148).by Jeffrey Thomas Evernham.M.S

Hybrid receiver study

The results are presented of a 4 month study to design a hybrid analog/digital receiver for outer planet mission probe communication links. The scope of this study includes functional design of the receiver; comparisons between analog and digital processing; hardware tradeoffs for key components including frequency generators, A/D converters, and digital processors; development and simulation of the processing algorithms for acquisition, tracking, and demodulation; and detailed design of the receiver in order to determine its size, weight, power, reliability, and radiation hardness. In addition, an evaluation was made of the receiver's capabilities to perform accurate measurement of signal strength and frequency for radio science missions

An asynchronous,low-power architecture for interleaved neural stimulation, using envelope and phase information

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 122-124).This thesis describes a low-power cochlear-implant processor chip and a charge-balanced stimulation chip that together form a complete processing-and-stimulation cochlear-implant system. The processor chip uses a novel Asynchronous Interleaved Stimulation (AIS) algorithm that preserves phase and amplitude cues in its spectral input while simultaneously minimizing electrode interactions and lowering average stimulation power per electrode. The stimulator chip obviates the need for large D.C. blocking capacitors in neural implants to achieve highly precise charge-balanced stimulation, thus lowering the size and cost of the implant. Thus, this thesis suggests that significant performance, power and cost improvements in the current generation of cochlear implants may be simultaneously possible. The 16-channel ~90 square mm AIS processor chip was built in a 1.5[mu]m VLSI process and consumed 107[mu]W of power over and above that of its analog spectral processing front end, which consumed 250gtW and which has been previously described. The AIS processor was found to faithfully mimic MATLAB implementations of the AIS algorithm. Two perceptual tests of the AIS algorithm with normal-hearing listeners verified that AIS signal reconstructions enabled better melody and speech recognition in noise than traditional envelope-only vocoder simulations of cochlear-implant processing. The average firing rate of the AIS processor was found to be significantly lower than in traditional synchronous stimulators, suggesting that the AIS algorithm and processor can potentially save power and improve hearing performance in cochlear-implant users. The stimulator chip was built in a 0.7glm high-voltage VLSI process and performed dynamic current balancing followed by a shorting phase.(cont.) It achieved <6nA of average DC current error, well below the targeted safety limit of 25nA for cochlear-implant patients. On +6 and -9V rails, the power consumption of a single channel of this chip was 47[mu]W when biasing power is shared by 16 channels. It puts out a charge-balanced stimulation pulse whenever it receives an asynchronous input signal from an AIS processor encoding phase information and 7-bit amplitude information, thus making the AIS processor chip and stimulator chip fully compatible in the cochlear-implant system. The AIS algorithm and charge-balancing circuits described in this work may be useful in other nerve-stimulation prosthetics where good fidelity in input-information encoding, minimization of electrode interactions, low-power strategies for stimulation, and compact charge-balanced stimulation are also important.by Ji-Jon Sit.Ph.D

MIT Space Engineering Research Center

The Space Engineering Research Center (SERC) at MIT, started in Jul. 1988, has completed two years of research. The Center is approaching the operational phase of its first testbed, is midway through the construction of a second testbed, and is in the design phase of a third. We presently have seven participating faculty, four participating staff members, ten graduate students, and numerous undergraduates. This report reviews the testbed programs, individual graduate research, other SERC activities not funded by the Center, interaction with non-MIT organizations, and SERC milestones. Published papers made possible by SERC funding are included at the end of the report

MICROWAVE FILTERS FOR NEXT GENERATION RADIO FREQUENCY TRANSCEIVERS

Increased data rates in wireless communications enforce unprecedented performance metrics on the front-end filters to operate in crowded spectral bands. These requirements include strong selectivity, low insertion loss, and good out-of-band (OOB) rejection in addition to the applicability in complementary metal oxide semiconductor (CMOS) integrated circuit layouts. The acoustic wave (AW) resonator based filter design technology has gained a very important role in the on-chip filter design techniques due to chip-scale physical resonator sizes and the ability of achieving high quality factor values at microwave frequencies. However, conventional synthesis methods used in the design of AW resonator based microwave filters suffer from limited achievable fractional bandwidth (FBW) and weak OOB rejection. The origin of these issues is the limitations on increasing the electromechanical coupling coefficient (kt2) of the resonators, which is an intrinsic property of the piezoelectric material in its design. This dissertation proposes a new class of hybrid acoustic-electromagnetic (Hybrid-ACEM) filters to overcome both of the aforementioned limitations of AW resonator-based filters. In other words, the main goal of this new topology is to maximize the ratio between the achievable FBW and the required kt2. This is achieved by employing one or two electromagnetic (EM) resonators that are placed at purposefully selected stages within the design. In addition, cross-coupling mechanisms are systematically used to reduce the required electromechanical coupling coefficient in certain filter orders. Altogether, the proposed method can achieve much larger FBW values and stronger OOB rejection compared to the conventionally synthesized ladder acoustic wave filters. The effect of finite quality factor of the EM resonators is analyzed. A new algorithm to convert extracted-pole sections to Butterworth-Van-Dyke (BVD) model for large FBW values is also presented. It has been shown in the simulations that FBW-to-kt2 ratios of four or above is achievable with this method. As a proof-of-concept, a sixth-order hybrid canonical prototype with a center frequency of 2.67 GHz and 11.2% FBW is designed and fabricated. The acoustic wave resonators used in the fabrication have kt2 values of 3.5%. The fabricated prototype proves the validity of the proposed method for achieving FBW values of 30% with required kt2 values of 7.5%, which is available with the common aluminum nitride (AlN) based bulk acoustic wave resonator technologies of today. The developed technique opens a new pathway to reduce the limitations of integrating microwave filters for future fully on-chip microwave transceivers