Minority Carrier Tunneling and Stress-Induced Leakage Current for p+ gate MOS Capacitors with Poly-Si and PolySi0.7Ge0.3 Gate Material

In this paper the I-V conduction mechanism for gate injection (-V g), Stress-Induced Leakage Current (SILC) characteristics and time-to-breakdown (tbd) of PMOS capacitors with p+-poly-Si and poly-SiGe gate material on 5.6, 4.8 and 3.1 nm oxide thickness are studied. A model based on Minority Carrier Tunneling (MCT) from the gate is proposed for the I-V and SILC characteristics at -Vg of our devices. Time-to-breakdown data are presented and discusse

Gate Stack Dielectric Degradation of Rare-Earth Oxides Grown on High Mobility Ge Substrates

We report on the dielectric degradation of Rare-Earth Oxides (REOs), when used as interfacial buffer layers together with HfO2 high-k films (REOs/HfO2) on high mobility Ge substrates. Metal-Oxide-Semiconductor (MOS) devices with these stacks,show dissimilar charge trapping phenomena under varying levels of Constant- Voltage-Stress (CVS) conditions, which also influences the measured densities of the interface (Nit) and border (NBT) traps. In the present study we also report on C-Vg hysteresis curves related to Nit and NBT. We also propose a new model based on Maxwell-Wagner instabilities mechanism that explains the dielectric degradations (current decay transient behavior) of the gate stack devices grown on high mobility substrates under CVS bias from low to higher fields, and which is unlike to those used for other MOS devices. Finally, the time dependent degradation of the corresponding devices revealed an initial current decay due to relaxation, followed by charge trapping and generation of stress-induced leakage which eventually lead to hard breakdown after long CVS stressing.Comment: 19pages (double space), 7 figures, original research article, Submitted to JAP (AIP

Dielectric Breakdown in Chemical Vapor Deposited Hexagonal Boron Nitride

Insulating films are essential in multiple electronic devices because they can provide essential functionalities, such as capacitance effects and electrical fields. Two-dimensional (2D) layered materials have superb electronic, physical, chemical, thermal, and optical properties, and they can be effectively used to provide additional performances, such as flexibility and transparency. 2D layered insulators are called to be essential in future electronic devices, but their reliability, degradation kinetics, and dielectric breakdown (BD) process are still not understood. In this work, the dielectric breakdown process of multilayer hexagonal boron nitride (h-BN) is analyzed on the nanoscale and on the device level, and the experimental results are studied via theoretical models. It is found that under electrical stress, local charge accumulation and charge trapping/detrapping are the onset mechanisms for dielectric BD formation. By means of conductive atomic force microscopy, the BD event was triggered at several locations on the surface of different dielectrics (SiO2, HfO2, Al2O3, multilayer h-BN, and monolayer h-BN); BD-induced hillocks rapidly appeared on the surface of all of them when the BD was reached, except in monolayer h-BN. The high thermal conductivity of h-BN combined with the one-atom-thick nature are genuine factors contributing to heat dissipation at the BD spot, which avoids self-accelerated and thermally driven catastrophic BD. These results point to monolayer h-BN as a sublime dielectric in terms of reliability, which may have important implications in future digital electronic devices.Fil: Jiang, Lanlan. Soochow University; ChinaFil: Shi, Yuanyuan. Soochow University; China. University of Stanford; Estados UnidosFil: Hui, Fei. Soochow University; China. Massachusetts Institute of Technology; Estados UnidosFil: Tang, Kechao. University of Stanford; Estados UnidosFil: Wu, Qian. Soochow University; ChinaFil: Pan, Chengbin. Soochow University; ChinaFil: Jing, Xu. Soochow University; China. University of Texas at Austin; Estados UnidosFil: Uppal, Hasan. University of Manchester; Reino UnidoFil: Palumbo, Félix Roberto Mario. Comisión Nacional de Energía Atómica; Argentina. Universidad Tecnológica Nacional; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas; ArgentinaFil: Lu, Guangyuan. Chinese Academy of Sciences; República de ChinaFil: Wu, Tianru. Chinese Academy of Sciences; República de ChinaFil: Wang, Haomin. Chinese Academy of Sciences; República de ChinaFil: Villena, Marco A.. Soochow University; ChinaFil: Xie, Xiaoming. Chinese Academy of Sciences; República de China. ShanghaiTech University; ChinaFil: McIntyre, Paul C.. University of Stanford; Estados UnidosFil: Lanza, Mario. Soochow University; Chin

Double-gated graphene-based devices

We discuss transport through double gated single and few layer graphene devices. This kind of device configuration has been used to investigate the modulation of the energy band structure through the application of an external perpendicular electric field, a unique property of few layer graphene systems. Here we discuss technological details that are important for the fabrication of top gated structures, based on electron-gun evaporation of SiO$_2$. We perform a statistical study that demonstrates how --contrary to expectations-- the breakdown field of electron-gun evaporated thin SiO$_2$ films is comparable to that of thermally grown oxide layers. We find that a high breakdown field can be achieved in evaporated SiO$_2$ only if the oxide deposition is directly followed by the metallization of the top electrodes, without exposure to air of the SiO$_2$ layer.Comment: Replaced with revised version. To appear on New Journal of Physic

Fabrication and operation of a two-dimensional ion-trap lattice on a high-voltage microchip

Microfabricated ion traps are a major advancement towards scalable quantum computing with trapped ions. The development of more versatile ion-trap designs, in which tailored arrays of ions are positioned in two dimensions above a microfabricated surface, will lead to applications in fields as varied as quantum simulation, metrology and atom–ion interactions. Current surface ion traps often have low trap depths and high heating rates, because of the size of the voltages that can be applied to them, limiting the fidelity of quantum gates. Here we report on a fabrication process that allows for the application of very high voltages to microfabricated devices in general and use this advance to fabricate a two-dimensional ion-trap lattice on a microchip. Our microfabricated architecture allows for reliable trapping of two-dimensional ion lattices, long ion lifetimes, rudimentary shuttling between lattice sites and the ability to deterministically introduce defects into the ion lattice

Electrical current distribution across a metal-insulator-metal structure during bistable switching

Combining scanning electron microscopy (SEM) and electron-beam-induced current (EBIC) imaging with transport measurements, it is shown that the current flowing across a two-terminal oxide-based capacitor-like structure is preferentially confined in areas localized at defects. As the thin-film device switches between two different resistance states, the distribution and intensity of the current paths, appearing as bright spots, change. This implies that switching and memory effects are mainly determined by the conducting properties along such paths. A model based on the storage and release of charge carriers within the insulator seems adequate to explain the observed memory effect.Comment: 8 pages, 7 figures, submitted to J. Appl. Phy

Dielectric relaxation and Charge trapping characteristics study in Germanium based MOS devices with HfO2 /Dy2O3 gate stacks

In the present work we investigate the dielectric relaxation effects and charge trapping characteristics of HfO2 /Dy2O3 gate stacks grown on Ge substrates. The MOS devices have been subjected to constant voltage stress (CVS) conditions at accumulation and show relaxation effects in the whole range of applied stress voltages. Applied voltage polarities as well as thickness dependence of the relaxation effects have been investigated. Charge trapping is negligible at low stress fields while at higher fields (>4MV/cm) it becomes significant. In addition, we give experimental evidence that in tandem with the dielectric relaxation effect another mechanism- the so-called Maxwell-Wagner instability- is present and affects the transient current during the application of a CVS pulse. This instability is also found to be field dependent thus resulting in a trapped charge which is negative at low stress fields but changes to positive at higher fields.Comment: 27pages, 10 figures, 3 tables, regular journal contribution (accepted in IEEE TED, Vol.50, issue 10