Endoscopic inspection using a panoramic annular lens

The objective of this one year study was to design, build, and demonstrate a prototype system for cavity inspection. A cylindrical view of the cavity interior was captured in real time through a compound lens system consisting of a unique panoramic annular lens and a collector lens. Images, acquired with a digitizing camera and stored in a desktop computer, were manipulated using image processing software to aid in visual inspection and qualitative analysis. A detailed description of the lens and its applications is given

Hierarchical Memory Size Estimation for Loop Transformation and Data Memory Platform Optimization

In today’s embedded systems, the memory hierarchy is rapidly becoming a major bottleneck in terms of power, performance and area, due to the very large amount of (memory related) data need to be transferred and stored (temporarily). This is especially the case for portable multi-media applications systems. These applications are characterized by deep loop nests and multi-dimensional arrays at the high level. Due to the dramatically increasing size and complexity of system-on-a-chip (SoC) designs and stringent time-to-market requirement, the methodology and tools for chip design must be raised to the system level. Early analysis tools are particularly critical in enabling SoC designers to take full advantage of the many architectural options available. For memory optimization, the early high level techniques aim either to design an optimal memory platform for a given application or to optimize the application code in order to take advantage of the memory platform features, or even both. Loop transformation is such an important high level optimization technique. It modifies the execution order of loops and statements without changing the application functionality. Existing loop transformation algorithms are all performed based either on reduction of data access lifetime and on improvement in data locality and regularity to steer selection of loop transformations. These are, however, very abstract cost functions which do not represent the exact memory size requirement of the arrays and how the data will be mapped onto the memory platform later on. Existing algorithms all result in one final loop transformation solution. As different loop transformations may result in optimal utilization for different memory platform instances, ad-hoc decisions at this stage without estimating their impact on the actual hierarchy utilization can lead to a final sub-optimal solution. An evaluation of later design stages’ effort is hence required. On the other hand, there usually exist a huge number of loop transformation possibilities, the estimation is required to be performed repeatedly and its computation time of the estimation technique also becomes critical to make it useful during the loop transformation search space exploration. This dissertation proposes a memory footprint estimation methodology. An intra-array memory footprint estimation is performed first followed by an interarray estimation. In order to achieve a fast estimate to make it useful repeatedly during the early high level search space exploration, several techniques have been introduced. A fast intra-array memory footprint estimation is performed at the iteration domain based on the maximal lifetime of data accesses, which is defined by the maximal dependency vector. Two approaches, an ILP formulation and vertexes approach, have been introduced for achieving a fast maximal dependency vector calculation. The fast inter-array estimation has been achieved based on several Hanoi tower based approaches. A hierarchical memory size estimation methodology has also been proposed in this dissertation. It estimates the influence of any given sequence of loop transformation instances on the mapping of application data onto a hierarchical memory platform. As the exact memory platform instantiation is often not yet defined at this high level design stage, a platform independent estimation is introduced with a Pareto curve output for each loop transformation instance. It can steer the designer or an automatic steering tool to select all the interesting loop transformation instances that might later lead to low power data mapping for any of the many possible memory hierarchy instances. This is useful when the memory platform is not defined yet, or for a given memory hierarchy instance. It also allows to find the most appropriate low power memory hierarchy instance by performing an early power estimation of different memory hierarchy instances. Initially the source code is used as input for estimation, resulting in an initial approach. However, performing the estimation repeatedly from the source code is too slow for the large loop transformation search space exploration. An incremental approach, based on local updating of the previous result, is thus introduced to handle sequences of different loop transformations. Several advanced techniques have also been used on these two approaches in order to perform a fast estimation, such as bounding box geometrical model based data reuse analysis, platform independent memory hierarchy layer assignment estimation, fast intra- and inter-array memory footprint estimation. The feasibility and usefulness of the methodologies are substantiated using several representative real-life application demonstrators. It shows for instance that the fast memory footprint estimation can be two order of magnitude faster than compared techniques while still achieving fairly accurate estimation result. For hierarchical memory size estimation methodology, the initial approach is two order of magnitude faster than the compared technique and the incremental approach is another two order of magnitude faster than the initial approach, which can just take a few milliseconds. The fast computation time of the incremental approach make it feasible to be used repeatedly during the loop transformation exploration over a very large number of possibilities. Furthermore, prototype CAD tools has been developed that includes mast parts of the methodologies

FPGA-based real-time moving target detection system for unmanned aerial vehicle application

Moving target detection is the most common task for Unmanned Aerial Vehicle (UAV) to find and track object of interest from a bird's eye view in mobile aerial surveillance for civilian applications such as search and rescue operation. The complex detection algorithm can be implemented in a real-time embedded system using Field Programmable Gate Array (FPGA). This paper presents the development of real-time moving target detection System-on-Chip (SoC) using FPGA for deployment on a UAV. The detection algorithm utilizes area-based image registration technique which includes motion estimation and object segmentation processes. The moving target detection system has been prototyped on a low-cost Terasic DE2-115 board mounted with TRDB-D5M camera. The system consists of Nios II processor and stream-oriented dedicated hardware accelerators running at 100 MHz clock rate, achieving 30-frame per second processing speed for 640 × 480 pixels' resolution greyscale videos

A Comprehensive Survey on Particle Swarm Optimization Algorithm and Its Applications

Particle swarm optimization (PSO) is a heuristic global optimization method, proposed originally by Kennedy and Eberhart in 1995. It is now one of the most commonly used optimization techniques. This survey presented a comprehensive investigation of PSO. On one hand, we provided advances with PSO, including its modifications (including quantum-behaved PSO, bare-bones PSO, chaotic PSO, and fuzzy PSO), population topology (as fully connected, von Neumann, ring, star, random, etc.), hybridization (with genetic algorithm, simulated annealing, Tabu search, artificial immune system, ant colony algorithm, artificial bee colony, differential evolution, harmonic search, and biogeography-based optimization), extensions (to multiobjective, constrained, discrete, and binary optimization), theoretical analysis (parameter selection and tuning, and convergence analysis), and parallel implementation (in multicore, multiprocessor, GPU, and cloud computing forms). On the other hand, we offered a survey on applications of PSO to the following eight fields: electrical and electronic engineering, automation control systems, communication theory, operations research, mechanical engineering, fuel and energy, medicine, chemistry, and biology. It is hoped that this survey would be beneficial for the researchers studying PSO algorithms

JUNO Conceptual Design Report

The Jiangmen Underground Neutrino Observatory (JUNO) is proposed to determine the neutrino mass hierarchy using an underground liquid scintillator detector. It is located 53 km away from both Yangjiang and Taishan Nuclear Power Plants in Guangdong, China. The experimental hall, spanning more than 50 meters, is under a granite mountain of over 700 m overburden. Within six years of running, the detection of reactor antineutrinos can resolve the neutrino mass hierarchy at a confidence level of 3-4$\sigma$, and determine neutrino oscillation parameters $\sin^2\theta_{12}$, $\Delta m^2_{21}$, and $|\Delta m^2_{ee}|$ to an accuracy of better than 1%. The JUNO detector can be also used to study terrestrial and extra-terrestrial neutrinos and new physics beyond the Standard Model. The central detector contains 20,000 tons liquid scintillator with an acrylic sphere of 35 m in diameter. $\sim$17,000 508-mm diameter PMTs with high quantum efficiency provide $\sim$75% optical coverage. The current choice of the liquid scintillator is: linear alkyl benzene (LAB) as the solvent, plus PPO as the scintillation fluor and a wavelength-shifter (Bis-MSB). The number of detected photoelectrons per MeV is larger than 1,100 and the energy resolution is expected to be 3% at 1 MeV. The calibration system is designed to deploy multiple sources to cover the entire energy range of reactor antineutrinos, and to achieve a full-volume position coverage inside the detector. The veto system is used for muon detection, muon induced background study and reduction. It consists of a Water Cherenkov detector and a Top Tracker system. The readout system, the detector control system and the offline system insure efficient and stable data acquisition and processing.Comment: 328 pages, 211 figure

Advances in Intelligent Robotics and Collaborative Automation

This book provides an overview of a series of advanced research lines in robotics as well as of design and development methodologies for intelligent robots and their intelligent components. It represents a selection of extended versions of the best papers presented at the Seventh IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications IDAACS 2013 that were related to these topics. Its contents integrate state of the art computational intelligence based techniques for automatic robot control to novel distributed sensing and data integration methodologies that can be applied to intelligent robotics and automation systems. The objective of the text was to provide an overview of some of the problems in the field of robotic systems and intelligent automation and the approaches and techniques that relevant research groups within this area are employing to try to solve them.The contributions of the different authors have been grouped into four main sections:• Robots• Control and Intelligence• Sensing• Collaborative automationThe chapters have been structured to provide an easy to follow introduction to the topics that are addressed, including the most relevant references, so that anyone interested in this field can get started in the area

Framework for a space shuttle main engine health monitoring system

A framework developed for a health management system (HMS) which is directed at improving the safety of operation of the Space Shuttle Main Engine (SSME) is summarized. An emphasis was placed on near term technology through requirements to use existing SSME instrumentation and to demonstrate the HMS during SSME ground tests within five years. The HMS framework was developed through an analysis of SSME failure modes, fault detection algorithms, sensor technologies, and hardware architectures. A key feature of the HMS framework design is that a clear path from the ground test system to a flight HMS was maintained. Fault detection techniques based on time series, nonlinear regression, and clustering algorithms were developed and demonstrated on data from SSME ground test failures. The fault detection algorithms exhibited 100 percent detection of faults, had an extremely low false alarm rate, and were robust to sensor loss. These algorithms were incorporated into a hierarchical decision making strategy for overall assessment of SSME health. A preliminary design for a hardware architecture capable of supporting real time operation of the HMS functions was developed. Utilizing modular, commercial off-the-shelf components produced a reliable low cost design with the flexibility to incorporate advances in algorithm and sensor technology as they become available

Integrated Microwave Photonic Processors using Waveguide Mesh Cores

Integrated microwave photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint and cost. Application Specific Photonic Integrated Circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long-development times and costly implementations. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable Microwave Photonic processor, where a common hardware implemented by the combination of microwave, photonic and electronic subsystems, realizes different functionalities through programming. Here, we propose the first-ever generic-purpose Microwave Photonic processor concept and architecture. This versatile processor requires a powerful end-to-end field-based analytical model to optimally configure all their subsystems as well as to evaluate their performance in terms of the radiofrequency gain, noise and dynamic range. Therefore, we develop a generic model for integrated Microwave Photonics systems. The key element of the processor is the reconfigurable optical core. It requires high flexibility and versatility to enable reconfigurable interconnections between subsystems as well as the synthesis of photonic integrated circuits. For this element, we focus on a 2-dimensional photonic waveguide mesh based on the interconnection of tunable couplers. Within the framework of this Thesis, we have proposed two novel interconnection schemes, aiming for a mesh design with a high level of versatility. Focusing on the hexagonal waveguide mesh, we explore the synthesis of a high variety of photonic integrated circuits and particular Microwave Photonics applications that can potentially be performed on a single hardware. In addition, we report the first-ever demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate a world-record number of functionalities on a single photonic integrated circuit enabling over 30 different functionalities from the 100 that could be potentially obtained with a simple seven hexagonal cell structure. The resulting device can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks as well as quantum information systems. Our work is an important step towards this paradigm and sets the base for a new era of generic-purpose photonic integrated systems.Los dispositivos integrados de fotónica de microondas ofrecen soluciones optimizadas para los sistemas de información y comunicación. Generalmente, están compuestos por diferentes arquitecturas en las que subsistemas ópticos y electrónicos se integran para optimizar las prestaciones, el consumo, el tamaño y el coste del dispositivo final. Hasta ahora, los circuitos/chips de propósito específico se han diseñado para proporcionar una funcionalidad concreta, requiriendo así un número considerable de iteraciones entre las etapas de diseño, fabricación y medida, que origina tiempos de desarrollo largos y costes demasiado elevados. Una alternativa, inspirada por las FPGA (del inglés Field Programmable Gate Array), es el procesador fotónico programable. Este dispositivo combina la integración de subsistemas de microondas, ópticos y electrónicos para realizar, mediante la programación de los mismos y sus interconexiones, diferentes funcionalidades. En este trabajo, proponemos por primera vez el concepto del procesador de propósito general, así como su arquitectura. Además, con el fin de diseñar, optimizar y evaluar las prestaciones básicas del dispositivo, hemos desarrollado un modelo analítico extremo a extremo basado en las componentes del campo electromagnético. El modelo desarrollado proporciona como resultado la ganancia, el ruido y el rango dinámico global para distintas configuraciones de modulación y detección, en función de los subsistemas y su configuración. El elemento principal del procesador es su núcleo óptico reconfigurable. Éste requiere un alto grado de flexibilidad y versatilidad para reconfigurar las interconexiones entre los distintos subsistemas y para sintetizar los circuitos para el procesado óptico. Para este subsistema, proponemos el diseño de guías de onda reconfigurables para la creación de mallados bidimensionales. En el marco de esta tesis, hemos propuesto dos nuevos nodos de interconexión óptica para mallas reconfigurables, con el objetivo de obtener un mayor grado de versatilidad. Una vez escogida la malla hexagonal para el núcleo del procesador, hemos analizado la configuración de un gran número de circuitos fotónicos integrados y de funcionalidades de fotónica de microondas. El trabajo se ha completado con la demonstración de la primera malla reconfigurable integrada en un chip de silicio, demostrando además la síntesis de 30 de las 100 funcionalidades que potencialmente se pueden obtener con la malla diseñada compuesta de 7 celdas hexagonales. Este hecho supone un record frente a los sistemas de propósito específico. El sistema puede aplicarse en diferentes campos como las comunicaciones, los sensores químicos y biomédicos, el procesado de señales, la gestión y procesamiento de redes y los sistemas de información cuánticos. El conjunto del trabajo realizado representa un paso importante en la evolución de este paradigma, y sienta las bases para una nueva era de dispositivos fotónicos de propósito general.Els dispositius integrats de Fotònica de Microones oferixen solucions optimitzades per als sistemes d'informació i comunicació. Generalment, estan compostos per diferents arquitectures en què subsistemes òptics i electrònics s'integren per a optimitzar les prestacions, el consum, la grandària i el cost del dispositiu final. Fins ara, els circuits/xips de propòsit específic s'han dissenyat per a proporcionar una funcionalitat concreta, requerint així un nombre considerable d'iteracions entre les etapes de disseny, fabricació i mesura, que origina temps de desenrotllament llargs i costos massa elevats. Una alternativa, inspirada per les FPGA (de l'anglés Field Programmable Gate Array), és el processador fotònic programable. Este dispositiu combina la integració de subsistemes de microones, òptics i electrònics per a realitzar, per mitjà de la programació dels mateixos i les seues interconnexions, diferents funcionalitats. En este treball proposem per primera vegada el concepte del processador de propòsit general, així com la seua arquitectura. A més, a fi de dissenyar, optimitzar i avaluar les prestacions bàsiques del dispositiu, hem desenrotllat un model analític extrem a extrem basat en els components del camp electromagnètic. El model desenrotllat proporciona com resultat el guany, el soroll i el rang dinàmic global per a distintes configuracions de modulació i detecció, en funció dels subsistemes i la seua configuració. L'element principal del processador és el seu nucli òptic reconfigurable. Este requerix un alt grau de flexibilitat i versatilitat per a reconfigurar les interconnexions entre els distints subsistemes i per a sintetitzar els circuits per al processat òptic. Per a este subsistema, proposem el disseny de guies d'onda reconfigurables per a la creació de mallats bidimensionals. En el marc d'esta tesi, hem proposat dos nous nodes d'interconnexió òptica per a malles reconfigurables, amb l'objectiu d'obtindre un major grau de versatilitat. Una vegada triada la malla hexagonal per al nucli del processador, hem analitzat la configuració d'un gran nombre de circuits fotónicos integrats i de funcionalitats de fotónica de microones. El treball s'ha completat amb la demostració de la primera malla reconfigurable integrada en un xip de silici, demostrant a més la síntesi de 30 de les 100 funcionalitats que potencialment es poden obtindre amb la malla dissenyada composta de 7 cèl·lules hexagonals. Este fet suposa un rècord enfront dels sistemes de propòsit específic. El sistema pot aplicarse en diferents camps com les comunicacions, els sensors químics i biomèdics, el processat de senyals, la gestió i processament de xarxes i els sistemes d'informació quàntics. El conjunt del treball realitzat representa un pas important en l'evolució d'este paradigma, i assenta les bases per a una nova era de dispositius fotónicos de propòsit general.Pérez López, D. (2017). Integrated Microwave Photonic Processors using Waveguide Mesh Cores [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/91232TESI

Applications of aerospace technology to petroleum exploration. Volume 2: Appendices

Participants in the investigation of problem areas in oil exploration are listed and the data acquisition methods used to determine categories to be studied are described. Specific aerospace techniques applicable to the tasks identified are explained and their costs evaluated