A Framework to Analyze Energy Efficiency of Multi-Band Spectrum Sensing Algorithms

Cognitive radio (CR) is a device which can detect wireless communication channels that are not in use and adapt its parameters intelligently. Networks with CRs use the available frequency bands much more efficiently and hence have higher data rates compare to traditional radios. Spectrum sensing is the class of techniques used by CRs to understand its wireless environment. Recent research on evaluating multi-band spectrum sensing algorithms is limited to only algorithm complexity and optimization; therefore, the primary goal of the study is to devise a novel framework that analyzes a multi-band spectrum sensing algorithm in terms of energy consumption and algorithm efficiency. The proposed structure leads to a comparison and evaluation of a large class of multi-band spectrum sensing algorithms. Multi-band spectrum sensing search methods such as linear, random and binary are evaluated for energy loss and detection performance using the proposed framework

Efficient Hardware Architecture for Cyclostationary Detector

Cognitive radio is one of the modern techniques which is evolved for utilising the unused spread spectrum effectively in wireless communication. In cognitive radio system the foremost concept is sensing the holes (spaces) in the frequency spectrum allotted and it facilitates a way that how effectively and efficiently the bandwidth is used by finding the spectrum holes in a designated spectrum. There are various methods available for sensing the spectrum and one such a sensing method is cyclostationary detection. The method of cyclostationary feature mainly focuses on detecting whether the primary user is present or absent. The threshold of a signal is calculated by cyclic cross-periodogram matrix of the corresponding signal to determine the presence of signal or noise. The difficulty in evaluating the targeted threshold is evaded by training an artificial neural network by extracted cyclostationary feature vectors which are obtained by FFT accumulation method. This paper proposes a hardware architecture for cyclostationary detection

Efficient Hardware Architecture for Cyclostationary Detector

Cognitive radio is one of the modern techniques which is evolved for utilising the unused spread spectrum effectively in wireless communication. In cognitive radio system the foremost concept is sensing the holes (spaces) in the frequency spectrum allotted and it facilitates a way that how effectively and efficiently the bandwidth is used by finding the spectrum holes in a designated spectrum. There are various methods available for sensing the spectrum and one such a sensing method is cyclostationary detection.  The method of cyclostationary feature mainly focuses on detecting whether the primary user is present or absent. The threshold of a signal is calculated by cyclic cross-periodogram matrix of the corresponding signal to determine the presence of signal or noise. The difficulty in evaluating the targeted threshold is evaded by training an artificial neural network by extracted cyclostationary feature vectors which are obtained by FFT accumulation method. This paper proposes a hardware architecture for cyclostationary detection

Wideband Sequential Spectrum Sensing with Varying Thresholds

In this contribution, time varying threshold sequential detectors are employed for energy detection-based spectrum sensing in low-SNR regimes. Sequential detection is proven to be faster (on average) than any other multi-sample detector for a set of given probabilities of detection and false-alarm. In this report, exact performance of a sequential detector for spectrum sensing is analyzed using the direct method. The theoretical results presented herein are verified with Monte-Carlo simulations. It is shown that for a SNR of −10 dB, among tests with Wald and triangular thresholds with similar probabilities of mis-detection and false-alarm, triangular performs 54% faster in terms of maximum detection time (90 percentile)

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

Development of self-organizing methods for radio spectrum sensing

A problem of wide-band radio spectrum analysis in real time was solved and presented in the dissertation. The goal of the work was to develop a spectrum sensing method for primary user emission detection in radio spectrum by investigating new signal feature extraction and intelligent decision making techniques. A solution of this problem is important for application in cognitive radio systems, where radio spectrum is analyzed in real time. In thesis there are reviewed currently suggested spectrum analysis methods, which are used for cognitive radio. The main purpose of these methods is to optimize spectrum description feature estimation in real-time systems and to select suitable classification threshold. For signal spectrum description analyzed methods used signal energy estimation, analyzed energy statistical difference in time and frequency. In addition, the review has shown that the wavelet transform can be used for signal pre-processing in spectrum sensors. For classification threshold selection in literature most common methods are based on statistical noise estimate and energy statistical change analysis. However, there are no suggested efficient methods, which let classification threshold to change adaptively, when RF environment changes. It were suggested signal features estimation modifications, which let to increase the efficiency of algorithm implementation in embedded system, by decreasing the amount of required calculations and preserving the accuracy of spectrum analysis algorithms. For primary signal processing it is suggested to use wavelet transform based features extraction, which are used for spectrum sensors and lets to increase accuracy of noisy signal detection. All primary user signal emissions were detected with lower than 1% false alarm ratio. In dissertation, there are suggested artificial neural network based methods, which let adaptively select classification threshold for the spectrum sensors. During experimental tests, there was achieved full signals emissions detection with false alarm ratio lower than 1%. It was suggested self organizing map structure modification, which increases network self-training speed up to 32 times. This self-training speed is achieved due to additional inner weights, which are added in to self organizing map structure. In self-training stage network structure changes especially fast and when topology, which is suited for given task, is reached, in further self-training iterations it can be disordered. In order to avoid this over-training, self-training process monitoring algorithms must be used. There were suggested original methods for self-training process control, which let to avoid network over-training and decrease self-training iteration quantity

Secure Transmission Design for Cognitive Radio Networks With Poisson Distributed Eavesdroppers

In this paper, we study physical layer security in an underlay cognitive radio (CR) network. We consider the problem of secure communication between a secondary transmitter-receiver pair in the presence of randomly distributed eavesdroppers under an interference constraint set by the primary user. For different channel knowledge assumptions at the transmitter, we design four transmission protocols to achieve the secure transmission in the CR network. We give a comprehensive performance analysis for each protocol in terms of transmission delay, security, reliability, and the overall secrecy throughput. Furthermore, we determine the optimal design parameter for each transmission protocol by solving the optimization problem of maximizing the secrecy throughput subject to both security and reliability constraints. Numerical results illustrate the performance comparison between different transmission protocols.ARC Discovery Projects Grant DP15010390

Digital Architectures for UWB Beamforming Using 2D IIR Spatio-Temporal Frequency-Planar Filters

A design method and an FPGA-based prototype implementation of massively parallel systolic-array VLSI architectures for 2nd-order and 3rd-order frequency-planar beam plane-wave filters are proposed. Frequency-planar beamforming enables highly-directional UWB RF beams at low computational complexity compared to digital phased-array feed techniques. The array factors of the proposed realizations are simulated and both high-directional selectivity and UWB performance are demonstrated. The proposed architectures operate using 2's complement finite precision digital arithmetic. The real-time throughput is maximized using look-ahead optimization applied locally to each processor in the proposed massively-parallel realization of the filter. From sensitivity theory, it is shown that 15 and 19-bit precision for filter coefficients results in better than 3% error for 2nd- and 3rd-order beam filters. Folding together with Ktimes multiplexing is applied to the proposed beam architectures such that throughput can be traded for K-fold lower complexity for realizing the 2-D fan filter banks. Prototype FPGA circuit implementations of these filters are proposed using a Virtex 6 xc6vsx475t-2ff1759 device. The FPGA-prototyped architectures are evaluated using area (A), critical path delay (T), and metrics AT and AT2. The L2 error energy is used as a metric for evaluating fixed-point noise levels and the accuracy of the finite precision digital arithmetic circuits