Monte Carlo Modeling of Spin FETs Controlled by Spin-Orbit Interaction

A method for Monte Carlo simulation of 2D spin-polarized electron transport in III-V semiconductor heterojunction FETs is presented. In the simulation, the dynamics of the electrons in coordinate and momentum space is treated semiclassically. The density matrix description of the spin is incorporated in the Monte Carlo method to account for the spin polarization dynamics. The spin-orbit interaction in the spin FET leads to both coherent evolution and dephasing of the electron spin polarization. Spin-independent scattering mechanisms, including optical phonons, acoustic phonons and ionized impurities, are implemented in the simulation. The electric field is determined self-consistently from the charge distribution resulting from the electron motion. Description of the Monte Carlo scheme is given and simulation results are reported for temperatures in the range 77-300 K.Comment: 18 pages, 7 figure

Gate-controlled reversible rectifying behaviour in tunnel contacted atomically-thin MoS2_{2} transistor

Atomically-thin 2D semiconducting materials integrated into van der Waals heterostructures have enabled architectures that hold great promise for next generation nanoelectronics. However, challenges still remain to enable their full acceptance as compliant materials for integration in logic devices. Two key-components to master are the barriers at metal/semiconductor interfaces and the mobility of the semiconducting channel, which endow the building-blocks of ${pn}$ diode and field effect transistor. Here, we have devised a reverted stacking technique to intercalate a wrinkle-free h-BN tunnel layer between MoS$_{2}$ channel and contacting electrodes. Vertical tunnelling of electrons therefore makes it possible to suppress the Schottky barriers and Fermi level pinning, leading to homogeneous gate-control of the channel chemical potential across the bandgap edges. The observed unprecedented features of ambipolar ${pn}$ to ${np}$ diode, which can be reversibly gate tuned, paves the way for future logic applications and high performance switches based on atomically thin semiconducting channel.Comment: 23 pages, 5 main figures + 9 SI figure

High magnetoresistance at room temperature in p-i-n graphene nanoribbons due to band-to-band tunneling effects

A large magnetoresistance effect is obtained at room-temperature by using p-i-n armchair-graphene-nanoribbon (GNR) heterostructures. The key advantage is the virtual elimination of thermal currents due to the presence of band gaps in the contacts. The current at B=0T is greatly decreased while the current at B>0T is relatively large due to the band-to-band tunneling effects, resulting in a high magnetoresistance ratio, even at room-temperature. Moreover, we explore the effects of edge-roughness, length, and width of GNR channels on device performance. An increase in edge-roughness and channel length enhances the magnetoresistance ratio while increased channel width can reduce the operating bias.Comment: http://dx.doi.org/10.1063/1.362445

A simple one-dimensional model for the explanation and analysis of GaAs MESFET behavior

The explanation of GaAs metal-semiconductor field effect transistor (MESFET) operation often involves the use of simplistic analytical formulae, which serve to obscure the more subtle physics of device action. The authors consider here a simple one-dimensional (1-D) model for GaAs MESFETs, which avoids more confusing numerical modeling schemes, yet still facilitates an analysis of the physical functionality of the device. The model takes into account current saturation due to either velocity saturation or channel pinch-off, the modulation of effective gate length and the series resistance of the regions beyond the gate. The results of the model have been compared to experimental data readily obtained from the literature, and the agreement has been shown to be goo

Characterization of the mechanisms of charge Trapping in GaN Vertical devices

In this master thesis a new type of transistor is analyzed: the GaN Vertical Fin FET Transistor. This kind of transistor is made on GaN, a wide bandgap semiconductor which is a promising material for the future power electronics . Fin FET Transistor is based on a fin-architecture and the current flows vertically through a GaN made nanometer-sized channel having a MOS stack on the sides. In this work different measurements are performed in order to see the variation of the threshold voltage and channel resistance of the transistor varying the fin width and external parameters such as temperature and exposure to UV-light. Oxide trapping phenomena are analysed by applying to the gate an increasing positive bias potential and for increasing periods of time. Simulations are performed in order to further analyze the results and give an extensive explanation of the charge trapping behaviour in different bias conditions.ope