Pressurizing Field-Effect Transistors of Few-Layer MoS2 in a Diamond Anvil Cell

Hydrostatic pressure applied using diamond anvil cells (DAC) has been widely explored to modulate physical properties of materials by tuning their lattice degree of freedom. Independently, electrical field is able to tune the electronic degree of freedom of functional materials via, for example, the field-effect transistor (FET) configuration. Combining these two orthogonal approaches would allow discovery of new physical properties and phases going beyond the known phase space. Such experiments are, however, technically challenging and have not been demonstrated. Herein, we report a feasible strategy to prepare and measure FETs in a DAC by lithographically patterning the nanodevices onto the diamond culet. Multiple-terminal FETs were fabricated in the DAC using few-layer MoS2 and BN as the channel semiconductor and dielectric layer, respectively. It is found that the mobility, conductance, carrier concentration, and contact conductance of MoS2 can all be significantly enhanced with pressure. We expect that the approach could enable unprecedented ways to explore new phases and properties of materials under coupled mechano-electrostatic modulation.Comment: 15 pages, 5 figure

High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

One of the major challenges in high-speed input/output (HSIO) links electrical validation is the physical layer (PHY) tuning process. Equalization techniques are employed to cancel any undesired effect. Typical industrial practices require massive lab measurements, making the equalization process very time consuming. In this paper, we exploit the Broyden-based input space mapping (SM) algorithm to efficiently optimize the PHY tuning receiver (Rx) equalizer settings for a SATA Gen 3 channel topology. We use a good-enough surrogate model as the coarse model, and an industrial post-silicon validation physical platform as the fine model. A map between the coarse and the fine model Rx equalizer settings is implicitly built, yielding an accelerated SM-based optimization of the PHY tuning process

Balancing ion parameters and fluorocarbon chemical reactants for SiO2 pattern transfer control using fluorocarbon-based atomic layer etching

In manufacturing, etch profiles play a significant role in device patterning. Here, the authors present a study of the evolution of etch profiles of nanopatterned silicon oxide using a chromium hard mask and a CHF3/Ar atomic layer etching in a conventional inductively coupled plasma tool. The authors show the effect of substrate electrode temperature, chamber pressure, and electrode forward power on the etch profile evolution of nanopatterned silicon oxide. Chamber pressure has an especially significant role, with lower pressure leading to lower etch rates and higher pattern fidelity. The authors also find that at higher electrode forward power, the physical component of etching increases and more anisotropic etching is achieved. By carefully tuning the process parameters, the authors are able to find the best conditions to achieve aspect-ratio independent etching and high fidelity patterning, with an average sidewall angle of 87° ± 1.5° and undercut values as low as 3.7 ± 0.5% for five trench sizes ranging from 150 to 30 nm. Furthermore, they provide some guidelines to understand the impact of plasma parameters on plasma ion distribution and thus on the atomic layer etching process

Atomic Layer Deposition to Fine-Tune the Surface Properties and Diameters of Fabricated Nanopores

Atomic layer deposition of alumina enhanced the molecule sensing characteristics of fabricated nanopores by fine-tuning their surface properties, reducing 1/f noise, neutralizing surface charge to favor capture of DNA and other negative polyelectrolytes, and controlling the diameter and aspect ratio of the pores with near single Ångstrom precision. The control over the chemical and physical nature of the pore surface provided by atomic layer deposition produced a higher yield of functional nanopore detectors.Molecular and Cellular BiologyPhysicsChemistry and Chemical BiologyEngineering and Applied Science

Free spectral range electrical tuning of a high quality on-chip microcavity

Reconfigurable photonic circuits have applications ranging from next-generation computer architectures to quantum networks, coherent radar and optical metamaterials. However, complete reconfigurability is only currently practical on millimetre-scale device footprints. Here, we overcome this barrier by developing an on-chip high quality microcavity with resonances that can be electrically tuned across a full free spectral range (FSR). FSR tuning allows resonance with any source or emitter, or between any number of networked microcavities. We achieve it by integrating nanoelectronic actuation with strong optomechanical interactions that create a highly strain-dependent effective refractive index. This allows low voltages and sub-nanowatt power consumption. We demonstrate a basic reconfigurable photonic network, bringing the microcavity into resonance with an arbitrary mode of a microtoroidal optical cavity across a telecommunications fibre link. Our results have applications beyond photonic circuits, including widely tuneable integrated lasers, reconfigurable optical filters for telecommunications and astronomy, and on-chip sensor networks.Comment: Main text: 7 pages, 3 figures. Supplementary information: 7 pages, 9 figure

On the Trade-Off Between Quality Factor and Tuning Ratio in Tunable High-Frequency Capacitors

A benchmark of tunable and switchable devices at microwave frequencies is presented on the basis of physical limitations to show their potential for reconfigurable cellular applications. Performance limitations are outlined for each given technology focusing on the quality factor (Q) and tuning ratio (eta) as figures of merit. The state of the art in terms of these figures of merit of several tunable and switchable technologies is visualized and discussed. If the performance of these criteria is not met, the application will not be feasible. The quality factor can typically be traded off for tuning ratio. The benchmark of tunable capacitor technologies shows that transistor-switched capacitors, varactor diodes, and ferroelectric varactors perform well at 2 GHz for tuning ratios below 3, with an advantage for GaAs varactor diodes. Planar microelectromechanical capacitive switches have the potential to outperform all other technologies at tuning ratios higher than 8. Capacitors based on tunable dielectrics have the highest miniaturization potential, whereas semiconductor devices benefit from the existing manufacturing infrastructure