Design of an integrated analog controller for a Class-D Audio Amplifier

An integrated analog controller for a self-oscillating class-D audio power amplifier is designed in a 0.35 μm CMOS technology for a 3.3 Volt power supply. It is intended to be used with an external output stage and passive filter, for medium power applications of upto a few 100 Watts. The controller was optimized with regard to its loop gain to suppress the distortion of the output stage. In typical commercially available output stages, the distortion is dominated by dead time effects and the THD can be as low as 20 dB. The controller uses self-oscillation to generate the carrier. To control the self-oscillation a second order phase shift network is embedded in the loop. To increase the loop gain a fifth-order loop filter is added. For a switching frequency of 400kHz the controller achieves a loop gain of 51 dB, nearly flat over the audio band. For reasons of flexibility, the order of the controller is made programmable, as well as the dead time and the delay in the loop. Full spice simulations of the controller combined with an external 120 Watt output stage indicate that a THD of upto 80 dB (better than 0.01%) can be obtained even under the worst case condition of a dead time of 50 ns

GaN vs. Si for Class D Audio Applications

The demands and applications of modern power electronics are quickly moving past the maximum performance capabilities of Silicon devices. As the processing of Wide Bandgap (WBG) materials matures and the commercial availability of WBG devices grows, circuit designers are exploring many applications to exploit the performance benefits over traditional Silicon devices. This work examines the under-explored application of GaN-based Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available Silicon MOSFETs. It is suggested that GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound

Towards Active Transducers

One of the trends within consumer audio systems is the requirement for surround sound systems, based on 5-7 or even more audio channels, resulting in the same number of power amplifier channels and loudspeakers for each system. Most systems on the market today are based on linear amplifiers techniques developed in the middle of last century, which is surprising when the last few decades’ development within the audio source material, that is CD, DVD and SACD to mention the most popular, are taken into account. Audio performance of linear amplifiers has reached a level suitable for high quality audio reproduction many product generations ago, but the biggest disadvantages are still left untouched; power efficiency, size and cost. With today’s technology, high efficient switch mode, or class D audio amplifiers based on pulse width modulation, PWM, are realizable. With the class D technology, consumer audio systems can benefit significantly from the highly increased power efficiency of class D amplifiers as well as their reduced size without need for bulky heat sinks, and also very important, low cost. The topic of this project is a total integration of switch mode audio amplifiers and loudspeakers into one single unit using the voice coil of the loudspeaker as output filter for the amplifier, with a perspective of highly reduced system power losses, system size and cost. Standard switch mode audio amplifiers and loudspeakers on the market are designed for use in traditional audio systems, and cannot without severe modifications be used for the integrated system without sacrifice of power efficiency. For this reason techniques for dedication of amplifier and loudspeaker for the specific purpose of the integration has been of major importance in this project. This thesis is a fundamental study of the loss mechanisms in loudspeakers and amplifiers and suggestions for optimizations are made to reduce the system power losses and cost without compromising the audio performance. Some of the results obtained in the project are redesign of and optimization of the parts in a loudspeaker, so the function of output filter for the amplifier can be obtained without significant power losses. Guidelines for dedication of speaker and amplifier to the integration process with significantly lower system power losses are also given. Furthermore, the work done in the project has resulted in new switch mode amplifier topologies, with very high audio performance realizable at a very low cost

High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques

In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5μs with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab