21 research outputs found

    Design and investigation of nanometric and submicron integrated circuits for voltage and digital controlled oscillators

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    Disertacijoje nagrinėjama LC-ĮVG ir LC-SVG, architektūros, modeliai bei jų kūrimas taikant nanometrines ir submikronines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad tinkamos architektūros parinkimas ir integrinių grandynų technologijų taikymas įgalina sukurti reikiamų parametrų ir kokybės 2–10 GHz įtampa ir skaitmeniniu būdu valdomus generatorius nanometriniuose ir submikroniniuose integriniuose grandynuose. Darbo tikslas – sukurti 2–10 GHz LC-ĮVG ir LC-SVG blokus nanometrinėse bei submikroninėse KMOP integrinių grandynų technologijose, leidžiančius pasiekti reikiamus parametrus skirtus daugiastandarčiams daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams iki 10 GHz. Darbe išspręsti tokie uždaviniai: ištirtos LC-ĮVG ir LC-SVG architektūros skirtingose integrinių grandynų KMOP technologijose ir parinkta optimali architektūra integrinių grandynų sukūrimui, pasiūlytos naujos kokybės funkcijos skirtos LC-ĮVG ir LC-SVG palyginamajai analizei, sukurti ir ištirti LC-ĮVG ir LC-SVG integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatūros ir autoriaus publikacijų disertacijos tema sąrašai ir trys priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma tyrimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, ginamieji teiginiai. Įvado pabaigoje pristatomos disertacijos tema autoriaus paskelbtos publikacijos ir pranešimai konferencijose bei disertacijos struktūra. Pirmajame skyriuje analizuojamos dažnio generatorių architektūros, jų pritaikymas bei jų pagrindiniai parametrai. Pateikiami pagrindiniai dažnio generatorių parametrai. Apžvelgiamos kokybės funkcijos, nusakančios dažnio generatorių pagrindinius parametrus skirtus palyginamajai analizei. Antrajame skyriuje pateikiamos naujos FOMTT FOMT2 kokybės funkcijos, kuriomis remiantis vertinami valdomo dažnio generatorių pagrindiniai parametrai palyginamajai analizei. Taip pat pateikiami induktyvumo ritės kokybės gerinimo būdai. Trečiajame skyriuje, taikant kompiuterinių skaičiavimų ir eksperimentinius metodus yra kuriami ir tiriami įtampa ir skaitmeniniu būdu valdomų generatorių bei papildomų blokų integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 2 – mokslo žurnaluose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 3 – tarptautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analy-tics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duomenų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti dvylikoje mokslinių konferencijų Lietuvoje ir užsienyje.Disertacij

    Design and investigation of nanometric integrated circuits for all-digital frequency synthesisers

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    Disertacijoje nagrinėjami daugiajuosčių dažnio sintezatorių blokai, modeliai bei jų kūrimas taikant nanometrines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad taikant nanometrines technologijas visiškai skaitmeniniai dažnio sintezatoriai įgalina gauti parametrus, reikiamus daugiajuosčiams belai- džio ryšio siųstuvams-imtuvams. Darbo tikslas – sukurti visiškai skaitmeninio dažnio sintezatoriaus blokus, kuriuos naudojant galima pasiekti reikiamus sinte- zatoriaus, skirto daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams, paramet- rus taikant nanometrines integrinių grandynų gamybos technologijas. Darbe išsp- ręsti tokie uždaviniai: ištirtos dažnio sintezatorių struktūros ir sukurta struktūra, tinkama įgyvendinti taikant nanometrines technologijas, sukurti ir ištirti siūlomos struktūros sintezatorių sudarančių blokų modeliai ir integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū- ros ir autoriaus publikacijų disertacijos tema sąrašai ir keturi priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašo- mas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma ty- rimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, gi- namieji teiginiai bei disertacijos struktūra. Pirmajame skyriuje apžvelgiamos dažnio sintezatorių rūšys, aprašomi pag- rindiniai dažnio sintezatorių parametrai ir dažniausiai naudojamos kokybės funk- cijos. Apžvelgiami dažnio sintezatorių modeliai ir jų veikimas fazės ir dažnio sri- tyse. Aprašomi visiškai skaitmeninio dažnio sintezatoriaus triukšmų šaltiniai. Skyriaus pabaigoje suformuluojami disertacijos uždaviniai. Antrajame skyriuje pasiūlyta ir taikoma nauja kokybės funkcija, leidžianti at- likti daugiajuosčių dažnio sintezatorių palyginamąją analizę. Iškeliami reikalavi- mai pagrindiniams sintezatoriaus blokams, nagrinėjami laikinio skaitmeninio kei- tiklio skiriamosios gebos didinimo būdai, sukurtas naujas laikinio skaitmeninio keitiklio modelis. Siūloma dažnio sintezatoriaus struktūra daugiajuosčiams siųs- tuvams-imtuvams. Trečiajame skyriuje pagal iškeltus reikalavimus daugiajuosčio dažnio sinte- zatoriaus blokams, taikant kompiuterinių skaičiavimų ir eksperimentinius meto- dus yra kuriami ir tiriami laikinio skaitmeninio keitiklio, skaitmeniniu būdu val- domo generatoriaus bei skaitmeninio filtro integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 4 – mokslo žurna- luose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 1 – tarp- tautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analytics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duo- menų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti devyniose mokslinėse konferencijose Lietuvoje ir užsienyje

    Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

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    Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

    Analysis and design of low-power data converters

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    In a large number of applications the signal processing is done exploiting both analog and digital signal processing techniques. In the past digital and analog circuits were made on separate chip in order to limit the interference and other side effects, but the actual trend is to realize the whole elaboration chain on a single System on Chip (SoC). This choice is driven by different reasons such as the reduction of power consumption, less silicon area occupation on the chip and also reliability and repeatability. Commonly a large area in a SoC is occupied by digital circuits, then, usually a CMOS short-channel technological processes optimized to realize digital circuits is chosen to maximize the performance of the Digital Signal Proccessor (DSP). Opposite, the short-channel technology nodes do not represent the best choice for analog circuits. But in a large number of applications, the signals which are treated have analog nature (microphone, speaker, antenna, accelerometers, biopotential, etc.), then the input and output interfaces of the processing chip are analog/mixed-signal conversion circuits. Therefore in a single integrated circuit (IC) both digital and analog circuits can be found. This gives advantages in term of total size, cost and power consumption of the SoC. The specific characteristics of CMOS short-channel processes such as: • Low breakdown voltage (BV) gives a power supply limit (about 1.2 V). • High threshold voltage VTH (compared with the available voltage supply) fixed in order to limit the leakage power consumption in digital applications (of the order of 0.35 / 0.4V), puts a limit on the voltage dynamic, and creates many problems with the stacked topologies. • Threshold voltage dependent on the channel length VTH = f(L) (short channel effects). • Low value of the output resistance of the MOS (r0) and gm limited by speed saturation, both causes contribute to achieving a low intrinsic gain gmr0 = 20 to 26dB. • Mismatch which brings offset effects on analog circuits. make the design of high performance analog circuits very difficult. Realizing lowpower circuits is fundamental in different contexts, and for different reasons: lowering the power dissipation gives the capability to reduce the batteries size in mobile devices (laptops, smartphones, cameras, measuring instruments, etc.), increase the life of remote sensing devices, satellites, space probes, also allows the reduction of the size and weight of the heat sink. The reduction of power dissipation allows the realization of implantable biomedical devices that do not damage biological tissue. For this reason, the analysis and design of low power and high precision analog circuits is important in order to obtain high performance in technological processes that are not optimized for such applications. Different ways can be taken to reduce the effect of the problems related to the technology: • Circuital level: a circuit-level intervention is possible to solve a specific problem of the circuit (i.e. Techniques for bandwidth expansion, increase the gain, power reduction, etc.). • Digital calibration: it is the highest level to intervene, and generally going to correct the non-ideal structure through a digital processing, these aims are based on models of specific errors of the structure. • Definition of new paradigms. This work has focused the attention on a very useful mixed-signal circuit: the pipeline ADC. The pipeline ADCs are widely used for their energy efficiency in high-precision applications where a resolution of about 10-16 bits and sampling rates above hundreds of Mega-samples per second (telecommunication, radar, etc.) are needed. An introduction on the theory of pipeline ADC, its state of the art and the principal non-idealities that affect the energy efficiency and the accuracy of this kind of data converters are reported in Chapter 1. Special consideration is put on low-voltage low-power ADCs. In particular, for ADCs implemented in deep submicron technology nodes side effects called short channel effects exist opposed to older technology nodes where undesired effects are not present. An overview of the short channel effects and their consequences on design, and also power consuption reduction techniques, with particular emphasis on the specific techniques adopted in pipelined ADC are reported in Chapter 2. Moreover, another way may be undertaken to increase the accuracy and the efficiency of an ADC, this way is the digital calibration. In Chapter 3 an overview on digital calibration techniques, and furthermore a new calibration technique based on Volterra kernels are reported. In some specific applications, such as software defined radios or micropower sensor, some circuits should be reconfigurable to be suitable for different radio standard or process signals with different charateristics. One of this building blocks is the ADC that should be able to reconfigure the resolution and conversion frequency. A reconfigurable voltage-scalable ADC pipeline capable to adapt its voltage supply starting from the required conversion frequency was developed, and the results are reported in Chapter 4. In Chapter 5, a pipeline ADC based on a novel paradigm for the feedback loop and its theory is described

    Sincronização em sistemas integrados a alta velocidade

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    Doutoramento em Engenharia ElectrotécnicaA distribui ção de um sinal relógio, com elevada precisão espacial (baixo skew) e temporal (baixo jitter ), em sistemas sí ncronos de alta velocidade tem-se revelado uma tarefa cada vez mais demorada e complexa devido ao escalonamento da tecnologia. Com a diminuição das dimensões dos dispositivos e a integração crescente de mais funcionalidades nos Circuitos Integrados (CIs), a precisão associada as transições do sinal de relógio tem sido cada vez mais afectada por varia ções de processo, tensão e temperatura. Esta tese aborda o problema da incerteza de rel ogio em CIs de alta velocidade, com o objetivo de determinar os limites do paradigma de desenho sí ncrono. Na prossecu ção deste objectivo principal, esta tese propõe quatro novos modelos de incerteza com âmbitos de aplicação diferentes. O primeiro modelo permite estimar a incerteza introduzida por um inversor est atico CMOS, com base em parâmetros simples e su cientemente gen éricos para que possa ser usado na previsão das limitações temporais de circuitos mais complexos, mesmo na fase inicial do projeto. O segundo modelo, permite estimar a incerteza em repetidores com liga ções RC e assim otimizar o dimensionamento da rede de distribui ção de relógio, com baixo esfor ço computacional. O terceiro modelo permite estimar a acumula ção de incerteza em cascatas de repetidores. Uma vez que este modelo tem em considera ção a correla ção entre fontes de ruí do, e especialmente util para promover t ecnicas de distribui ção de rel ogio e de alimentação que possam minimizar a acumulação de incerteza. O quarto modelo permite estimar a incerteza temporal em sistemas com m ultiplos dom ínios de sincronismo. Este modelo pode ser facilmente incorporado numa ferramenta autom atica para determinar a melhor topologia para uma determinada aplicação ou para avaliar a tolerância do sistema ao ru ído de alimentação. Finalmente, usando os modelos propostos, são discutidas as tendências da precisão de rel ogio. Conclui-se que os limites da precisão do rel ogio são, em ultima an alise, impostos por fontes de varia ção dinâmica que se preveem crescentes na actual l ogica de escalonamento dos dispositivos. Assim sendo, esta tese defende a procura de solu ções em outros ní veis de abstração, que não apenas o ní vel f sico, que possam contribuir para o aumento de desempenho dos CIs e que tenham um menor impacto nos pressupostos do paradigma de desenho sí ncrono.Distributing a the clock simultaneously everywhere (low skew) and periodically everywhere (low jitter) in high-performance Integrated Circuits (ICs) has become an increasingly di cult and time-consuming task, due to technology scaling. As transistor dimensions shrink and more functionality is packed into an IC, clock precision becomes increasingly a ected by Process, Voltage and Temperature (PVT) variations. This thesis addresses the problem of clock uncertainty in high-performance ICs, in order to determine the limits of the synchronous design paradigm. In pursuit of this main goal, this thesis proposes four new uncertainty models, with di erent underlying principles and scopes. The rst model targets uncertainty in static CMOS inverters. The main advantage of this model is that it depends only on parameters that can easily be obtained. Thus, it can provide information on upcoming constraints very early in the design stage. The second model addresses uncertainty in repeaters with RC interconnects, allowing the designer to optimise the repeater's size and spacing, for a given uncertainty budget, with low computational e ort. The third model, can be used to predict jitter accumulation in cascaded repeaters, like clock trees or delay lines. Because it takes into consideration correlations among variability sources, it can also be useful to promote oorplan-based power and clock distribution design in order to minimise jitter accumulation. A fourth model is proposed to analyse uncertainty in systems with multiple synchronous domains. It can be easily incorporated in an automatic tool to determine the best topology for a given application or to evaluate the system's tolerance to power-supply noise. Finally, using the proposed models, this thesis discusses clock precision trends. Results show that limits in clock precision are ultimately imposed by dynamic uncertainty, which is expected to continue increasing with technology scaling. Therefore, it advocates the search for solutions at other abstraction levels, and not only at the physical level, that may increase system performance with a smaller impact on the assumptions behind the synchronous design paradigm

    Solid State Circuits Technologies

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    The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

    Reconfigurable electronics based on metal-insulator transition:steep-slope switches and high frequency functions enabled by Vanadium Dioxide

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    The vast majority of disruptive innovations in science and technology has been originated from the discovery of a new material or the way its properties have been exploited to create novel devices and systems. New advanced nanomaterials will have a lasting impact over the next decades, providing breakthroughs in all scientific domains addressing the main challenges faced by the world today, including energy efficiency, sustainability, climate and health. The electronics industry relied over the last decades on the miniaturization process based on the scaling laws of complementary metal-oxide semiconductors (CMOS). As this process is approaching fundamental limitations, new materials or physical principles must be exploited to replace or supplement CMOS technology. The aim of the work in this thesis is to propose the abrupt metal-insulator transition in functional oxides as a physical phenomenon enabling new classes of Beyond CMOS devices. In order to provide an experimental validation of the proposed designs, vanadium dioxide (VO2) has been selected among functional oxides exhibiting a metal-insulator transition, due to the possibility to operate at room temperature and the high contrast between the electrical properties of its two structural phases. A CMOS-compatible sputtering process for uniform large scale deposition of stoichiometric polycrystalline VO2 has been optimized, enabling high yield and low variability for the devices presented in the rest of the thesis. The high quality of the film has been confirmed by several electrical and structural characterization techniques. The first class of devices based on the MIT in VO2 presented in this work is the steep-slope electronic switch. A quantitative study of the slope of the electrically induced MIT (E-MIT) in 2-terminal VO2 switches is reported, including its dependence on temperature. Moreover, the switches present excellent ON-state conduction independently of temperature, suggesting MIT VO2 switches as promising candidates for steep-slope, highly conductive, temperature stable electronic switches. A novel design for the shape of the electrodes used in VO2 switches has been proposed, targeting a reduction in the actuation voltage necessary to induce the E-MIT. The electrothermal simulations addressing this effect have been validated by measurements. The potential of the MIT in VO2 for reconfigurable electronics in the microwave frequency range has been expressed by the design, fabrication and characterization of low-loss, highly reliable, broadband VO2 radio-frequency (RF) switches, novel VO2 tunable capacitors and RF tunable filters. The newly proposed tunable capacitors overcome the frequency limitations of conventional VO2 RF switches, enabling filters working at a higher frequency range than the current state-of-the-art. An alternative actuation method for the tunable capacitors has been proposed by integrating microheaters for local heating of the VO2 region, and the design tradeoffs have been discussed by coupled electrothermal and electromagnetic simulations. The last device presented in this work operates in the terahertz (THz) range; the MIT in VO2 has been exploited to demonstrate for the first time the operation of a modulated scatterer (MST) working at THz frequencies. The proposed MST is the first THz device whose working principle is based on the actuation of a single VO2 junction, in contrast to commonly employed VO2 metasurfaces

    Accurate quantum transport modelling and epitaxial structure design of high-speed and high-power In0.53Ga0.47As/AlAs double-barrier resonant tunnelling diodes for 300-GHz oscillator sources

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    Terahertz (THz) wave technology is envisioned as an appealing and conceivable solution in the context of several potential high-impact applications, including sixth generation (6G) and beyond consumer-oriented ultra-broadband multi-gigabit wireless data-links, as well as highresolution imaging, radar, and spectroscopy apparatuses employable in biomedicine, industrial processes, security/defence, and material science. Despite the technological challenges posed by the THz gap, recent scientific advancements suggest the practical viability of THz systems. However, the development of transmitters (Tx) and receivers (Rx) based on compact semiconductor devices operating at THz frequencies is urgently demanded to meet the performance requirements calling from emerging THz applications. Although several are the promising candidates, including high-speed III-V transistors and photo-diodes, resonant tunnelling diode (RTD) technology offers a compact and high performance option in many practical scenarios. However, the main weakness of the technology is currently represented by the low output power capability of RTD THz Tx, which is mainly caused by the underdeveloped and non-optimal device, as well as circuit, design implementation approaches. Indeed, indium phosphide (InP) RTD devices can nowadays deliver only up to around 1 mW of radio-frequency (RF) power at around 300 GHz. In the context of THz wireless data-links, this severely impacts the Tx performance, limiting communication distance and data transfer capabilities which, at the current time, are of the order of few tens of gigabit per second below around 1 m. However, recent research studies suggest that several milliwatt of output power are required to achieve bit-rate capabilities of several tens of gigabits per second and beyond, and to reach several metres of communication distance in common operating conditions. Currently, the shortterm target is set to 5−10 mW of output power at around 300 GHz carrier waves, which would allow bit-rates in excess of 100 Gb/s, as well as wireless communications well above 5 m distance, in first-stage short-range scenarios. In order to reach it, maximisation of the RTD highfrequency RF power capability is of utmost importance. Despite that, reliable epitaxial structure design approaches, as well as accurate physical-based numerical simulation tools, aimed at RF power maximisation in the 300 GHz-band are lacking at the current time. This work aims at proposing practical solutions to address the aforementioned issues. First, a physical-based simulation methodology was developed to accurately and reliably simulate the static current-voltage (IV ) characteristic of indium gallium arsenide/aluminium arsenide (In-GaAs/AlAs) double-barrier RTD devices. The approach relies on the non-equilibrium Green’s function (NEGF) formalism implemented in Silvaco Atlas technology computer-aided design (TCAD) simulation package, requires low computational budget, and allows to correctly model In0.53Ga0.47As/AlAs RTD devices, which are pseudomorphically-grown on lattice-matched to InP substrates, and are commonly employed in oscillators working at around 300 GHz. By selecting the appropriate physical models, and by retrieving the correct materials parameters, together with a suitable discretisation of the associated heterostructure spatial domain through finite-elements, it is shown, by comparing simulation data with experimental results, that the developed numerical approach can reliably compute several quantities of interest that characterise the DC IV curve negative differential resistance (NDR) region, including peak current, peak voltage, and voltage swing, all of which are key parameters in RTD oscillator design. The demonstrated simulation approach was then used to study the impact of epitaxial structure design parameters, including those characterising the double-barrier quantum well, as well as emitter and collector regions, on the electrical properties of the RTD device. In particular, a comprehensive simulation analysis was conducted, and the retrieved output trends discussed based on the heterostructure band diagram, transmission coefficient energy spectrum, charge distribution, and DC current-density voltage (JV) curve. General design guidelines aimed at enhancing the RTD device maximum RF power gain capability are then deduced and discussed. To validate the proposed epitaxial design approach, an In0.53Ga0.47As/AlAs double-barrier RTD epitaxial structure providing several milliwatt of RF power was designed by employing the developed simulation methodology, and experimentally-investigated through the microfabrication of RTD devices and subsequent high-frequency characterisation up to 110 GHz. The analysis, which included fabrication optimisation, reveals an expected RF power performance of up to around 5 mW and 10 mW at 300 GHz for 25 μm2 and 49 μm2-large RTD devices, respectively, which is up to five times higher compared to the current state-of-the-art. Finally, in order to prove the practical employability of the proposed RTDs in oscillator circuits realised employing low-cost photo-lithography, both coplanar waveguide and microstrip inductive stubs are designed through a full three-dimensional electromagnetic simulation analysis. In summary, this work makes and important contribution to the rapidly evolving field of THz RTD technology, and demonstrates the practical feasibility of 300-GHz high-power RTD devices realisation, which will underpin the future development of Tx systems capable of the power levels required in the forthcoming THz applications

    Advanced Radio Frequency Identification Design and Applications

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    Radio Frequency Identification (RFID) is a modern wireless data transmission and reception technique for applications including automatic identification, asset tracking and security surveillance. This book focuses on the advances in RFID tag antenna and ASIC design, novel chipless RFID tag design, security protocol enhancements along with some novel applications of RFID
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