Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s

In-system Jitter Measurement Based on Blind Oversampling Data Recovery

The paper describes a novel method for simple estimation of jitter contained in a received digital signal. The main objective of our research was to enable a non-invasive measurement of data link properties during a regular data transmission. To evaluate the signal quality we estimate amount of jitter contained in the received signal by utilizing internal signals of a data recovery circuit. The method is a pure digital algorithm suitable for implementation in any digital integrated circuit (ASIC or FPGA). It is based on a blind-oversampling data recovery circuit which is used in some receivers instead of a traditional PLL-based clock and data recovery (CDR) circuit. Combination of the described jitter measurement block and the data recovery block forms a very efficient input part of the digital receiver. In such configuration it is able to simultaneously perform both data communication (data recovery) and signal quality estimation (jitter measurement). The jitter measurement portion of the receiver requires no special connection of the received data signal. Thus the measured signal is not influenced by the measurement circuitry at all. To verify the method we performed a measurement on a laboratory free-space optics link. Results of the measurement are satisfactory and can be used for on-line channel analysis

Frequency domain laser velocimeter signal processor: A new signal processing scheme

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst

Digitized synchronous demodulator

A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and medicated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period. This measurement will not include error sources encountered in prior art synchronous demodulators using analog techniques such as offsets, charge injection errors, temperature drift, switching transients, settling time, analog to digital converter missing code, and linearity errors

Retrodirective transponder feasibility experiment

Test program on feasibility of digital phase measuring subsystem of pulse-coherent retrodirective transponde

Digital demodulator-correlator

An apparatus for demodulation and correlation of a code modulated 10 MHz signal is presented. The apparatus is comprised of a sample and hold analog-to-digital converter synchronized by a frequency coherent 40 MHz pulse to obtain four evenly spaced samples of each of the signal. Each sample is added or subtracted to or from one of four accumulators to or from the separate sums. The correlation functions are then computed. As a further feature of the invention, multipliers are each multiplied by a squarewave chopper signal having a period that is long relative to the period of the received signal to foreclose contamination of the received signal by leakage from either of the other two terms of the multipliers

Signal-to-noise ratio estimation in digital computer simulation of lowpass and bandpass systems with applications to analog and digital communications, volume 3

Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation

Hybrid computer Monte-Carlo techniques

Hybrid analog-digital computer systems for Monte Carlo method application