Analysis of first and second order binary quantized digital phase-locked loops for ideal and white Gaussian noise inputs

Specific configurations of first and second order all digital phase locked loops are analyzed for both ideal and additive white gaussian noise inputs. In addition, a design for a hardware digital phase locked loop capable of either first or second order operation is presented along with appropriate experimental data obtained from testing of the hardware loop. All parameters chosen for the analysis and the design of the digital phase locked loop are consistent with an application to an Omega navigation receiver although neither the analysis nor the design are limited to this application

Design techniques for radiation hardened-phase locked loops

Spacecrafts experience radiation in the course of their operation and all electronic equipment on board these spacecrafts has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single event transients (SET) in phase-locked loops - an important circuit block for communication circuits and clock generation. The design of a digital phase-locked loop made tolerant to SET through redundancy and error correction techniques has been described. Digital phase-locked loops can also incorporate self-calibration techniques to compensate for the effects of TID. A linear analysis is presented for the design of digital phase-locked loops. This digital phase-locked loop was fabricated in the Honeywell 0.35 μm SOI CMOS process.Keywords: Phase-locked loops, Radiation hardene

Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters

The purpose of the paper is to introduce the Dynamic Phasor Modelling (DPM) approach for stability investigation and control design of single-phase Phase Locked Loops PLLs. The aim is to identify the system instabilities not predicted using the existent analysis and design methods based on the simplified average model approach

Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations and experiments

Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions. The inherently small laser wavelength allows to measure distance variations with extremely high precision by interfering a reference beam with a measurement beam. The readout of such interferometers is often based on tracking phasemeters, able to measure the phase of an incoming beatnote with high precision over a wide range of frequencies. The implementation of such phasemeters is based on all digital phase-locked loops, hosted in FPGAs. Here we present a precise model of an all digital phase locked loop that allows to design such a readout algorithm and we support our analysis by numerical performance measurements and experiments with analog signals.Comment: 17 pages, 6 figures, accepted for publication in CQ

A comparison of methods for DPLL loop filter design

Four design methodologies for loop filters for a class of digital phase-locked loops (DPLLs) are presented. The first design maps an optimum analog filter into the digital domain; the second approach designs a filter that minimizes in discrete time weighted combination of the variance of the phase error due to noise and the sum square of the deterministic phase error component; the third method uses Kalman filter estimation theory to design a filter composed of a least squares fading memory estimator and a predictor. The last design relies on classical theory, including rules for the design of compensators. Linear analysis is used throughout the article to compare different designs, and includes stability, steady state performance and transient behavior of the loops. Design methodology is not critical when the loop update rate can be made high relative to loop bandwidth, as the performance approaches that of continuous time. For low update rates, however, the miminization method is significantly superior to the other methods

Frequency division using cascaded phase-locked loops

In many practical communication systems it is necessary to generate phase coherent subharmonics of an input tone. A useful system for accomplishing this task is a system of phase-locked loops in cascade. It is shown that when the feed-forward function is matched, the phase error of the second loop is zero. Analytical analysis and computer simulation prove that the minimum time to achieve phase-lock is obtained when the feed-forward function is matched. Under this condition, necessary design parameters are determined with ease --Abstract, page i

High resolution angular sensor

Specifications for the pointing stabilization system of the large space telescope were used in an investigation of the feasibility of reducing ring laser gyro output quantization to the sub-arc-second level by the use of phase locked loops and associated electronics. Systems analysis procedures are discussed and a multioscillator laser gyro model is presented along with data on the oscillator noise. It is shown that a second order closed loop can meet the measurement noise requirements when the loop gain and time constant of the loop filter are appropriately chosen. The preliminary electrical design is discussed from the standpoint of circuit tradeoff considerations. Analog, digital, and hybrid designs are given and their applicability to the high resolution sensor is examined. the electrical design choice of a system configuration is detailed. The design and operation of the various modules is considered and system block diagrams are included. Phase 1 and 2 test results using the multioscillator laser gyro are included

A compilation of results pertaining to the behavior of phase locked loops

State-of-the art on phase locked loops PLL is reported by summarizing some specific results. Following a statement of the overall analysis and design objectives, results are presented in a format identifying working terminology, inherent assumptions, and references for each result. The use of PLL in tracking, synchronization, and demodulation is reemphasized, as well as the mathematical challenge involved in solving nonlinear stochastic differential equations