50 research outputs found
Random induced subgraphs of Cayley graphs induced by transpositions
In this paper we study random induced subgraphs of Cayley graphs of the
symmetric group induced by an arbitrary minimal generating set of
transpositions. A random induced subgraph of this Cayley graph is obtained by
selecting permutations with independent probability, . Our main
result is that for any minimal generating set of transpositions, for
probabilities where , a random induced subgraph has a.s. a unique
largest component of size , where
is the survival probability of a specific branching process.Comment: 18 pages, 1 figur
Analysis of wormhole routings in cayley graphs of permutation groups.
Over a decade, a new class of switching technology, called wormhole routing, has been investigated in the multicomputer interconnection network field. Several classes of wormhole routing algorithms have been proposed. Most of the algorithms have been centered on the traditional binary hypercube, k-ary n-cube mesh, and torus networks. In the design of a wormhole routing algorithm, deadlock avoidance scheme is the main concern. Recently, new classes of networks called Cayley graphs of permutation groups are considered very promising alternatives. Although proposed Cayley networks have superior topological properties over the traditional network topologies, the design of the deadlock-free wormhole routing algorithm in these networks is not simple. In this dissertation, we investigate deadlock free wormhole routing algorithms in the several classes of Cayley networks, such as complete-transposition and star networks. We evaluate several classes of routing algorithms on these networks, and compare the performance of each algorithm to the simulation study. Also, the performances of these networks are compared to the traditional networks. Through extensive simulation we found that adaptive algorithm outperformed deterministic algorithm in general with more virtual channels. On the network performance comparison, the complete transposition network showed the best performance among the similar sized networks, and the binary hypercube performed better compared to the star graph
Small-world interconnection networks for large parallel computer systems
The use of small-world graphs as interconnection networks of multicomputers is proposed and analysed in this work. Small-world interconnection networks are constructed by adding (or modifying) edges to an underlying local graph. Graphs with a rich local structure but with a large diameter are shown to be the most suitable candidates for the underlying graph. Generation models based on random and deterministic wiring processes are proposed and analysed. For the random case basic properties such as degree, diameter, average length and bisection width are analysed, and the results show that a fast transition from a large diameter to a small diameter is experienced when the number of new edges introduced is increased. Random traffic analysis on these networks is undertaken, and it is shown that although the average latency experiences a similar reduction, networks with a small number of shortcuts have a tendency to saturate as most of the traffic flows through a small number of links. An analysis of the congestion of the networks corroborates this result and provides away of estimating the minimum number of shortcuts required to avoid saturation. To overcome these problems deterministic wiring is proposed and analysed. A Linear Feedback Shift Register is used to introduce shortcuts in the LFSR graphs. A simple routing algorithm has been constructed for the LFSR and extended with a greedy local optimisation technique. It has been shown that a small search depth gives good results and is less costly to implement than a full shortest path algorithm. The Hilbert graph on the other hand provides some additional characteristics, such as support for incremental expansion, efficient layout in two dimensional space (using two layers), and a small fixed degree of four. Small-world hypergraphs have also been studied. In particular incomplete hypermeshes have been introduced and analysed and it has been shown that they outperform the complete traditional implementations under a constant pinout argument. Since it has been shown that complete hypermeshes outperform the mesh, the torus, low dimensional m-ary d-cubes (with and without bypass channels), and multi-stage interconnection networks (when realistic decision times are accounted for and with a constant pinout), it follows that incomplete hypermeshes outperform them as well
Quarc: an architecture for efficient on-chip communication
The exponential downscaling of the feature size has enforced a paradigm shift from computation-based design to communication-based design in system on chip development. Buses, the traditional communication architecture in systems on chip, are incapable of addressing the increasing bandwidth requirements of future large systems.
Networks on chip have emerged as an interconnection architecture offering unique solutions to the technological and design issues related to communication in future systems on chip. The transition from buses as a shared medium to networks on chip as a segmented medium has given rise to new challenges in system on chip realm.
By leveraging the shared nature of the communication medium, buses have been highly efficient in delivering multicast communication. The segmented nature of networks, however, inhibits the multicast messages to be delivered as efficiently by networks on chip. Relying on extensive research on multicast communication in parallel computers, several network on chip architectures have offered mechanisms to perform the operation, while conforming to resource constraints of the network on chip paradigm. Multicast communication in majority of these networks on chip is implemented by establishing a connection between source and all multicast destinations before the message transmission
commences. Establishing the connections incurs an overhead and, therefore, is not desirable; in particular in latency sensitive services such as cache coherence.
To address high performance multicast communication, this research presents Quarc, a novel network on chip architecture. The Quarc architecture targets an area-efficient, low power, high performance implementation. The thesis covers a detailed representation of
the building blocks of the architecture, including topology, router and network interface.
The cost and performance comparison of the Quarc architecture against other network on chip architectures reveals that the Quarc architecture is a highly efficient architecture.
Moreover, the thesis introduces novel performance models of complex traffic patterns, including multicast and quality of service-aware communication
Combinatorial Design and Analysis of Optimal Multiple Bus Systems for Parallel Algorithms.
This dissertation develops a formal and systematic methodology for designing optimal, synchronous multiple bus systems (MBSs) realizing given (classes of) parallel algorithms. Our approach utilizes graph and group theoretic concepts to develop the necessary model and procedural tools. By partitioning the vertex set of the graphical representation CFG of the algorithm, we extract a set of interconnection functions that represents the interprocessor communication requirement of the algorithm. We prove that the optimal partitioning problem is NP-Hard. However, we show how to obtain polynomial time solutions by exploiting certain regularities present in many well-behaved parallel algorithms. The extracted set of interconnection functions is represented by an edge colored, directed graph called interconnection function graph (IFG). We show that the problem of constructing an optimal MBS to realize an IFG is NP-Hard. We show important special cases where polynomial time solutions exist. In particular, we prove that polynomial time solutions exist when the IFG is vertex symmetric. This is the case of interest for the vast majority of important interconnection function sets, whether extracted from algorithms or correspond to existing interconnection networks. We show that an IFG is vertex symmetric if and only if it is the Cayley color graph of a finite group and its generating set Using this property, we present a particular scheme to construct a symmetric with minimum number of buses as well as minimum number of interfaces realizing a vertex symmetric IFG. We demonstrate several advantages of the optimal in terms of its symmetry, number of ports per processor, number of neighbors per processor, and the diameter. We also investigate the fault tolerant capabilities and performance degradation of in the case of a single bus failure, single driver failure, single receiver failure, and single processor failure. Further, we address the problem of designing an optimal MBS realizing a class of algorithms when the number of buses and/or processors in the target MBS are specified. The optimality criteria are maximizing the speed and minimizing the number of interfaces
Optical Wireless Data Center Networks
Bandwidth and computation-intensive Big Data applications in disciplines like social media, bio- and nano-informatics, Internet-of-Things (IoT), and real-time analytics, are pushing existing access and core (backbone) networks as well as Data Center Networks (DCNs) to their limits. Next generation DCNs must support continuously increasing network traffic while satisfying minimum performance requirements of latency, reliability, flexibility and scalability. Therefore, a larger number of cables (i.e., copper-cables and fiber optics) may be required in conventional wired DCNs. In addition to limiting the possible topologies, large number of cables may result into design and development problems related to wire ducting and maintenance, heat dissipation, and power consumption.
To address the cabling complexity in wired DCNs, we propose OWCells, a class of optical wireless cellular data center network architectures in which fixed line of sight (LOS) optical wireless communication (OWC) links are used to connect the racks arranged in regular polygonal topologies. We present the OWCell DCN architecture, develop its theoretical underpinnings, and investigate routing protocols and OWC transceiver design. To realize a fully wireless DCN, servers in racks must also be connected using OWC links. There is, however, a difficulty of connecting multiple adjacent network components, such as servers in a rack, using point-to-point LOS links. To overcome this problem, we propose and validate the feasibility of an FSO-Bus to connect multiple adjacent network components using NLOS point-to-point OWC links. Finally, to complete the design of the OWC transceiver, we develop a new class of strictly and rearrangeably non-blocking multicast optical switches in which multicast is performed efficiently at the physical optical (lower) layer rather than upper layers (e.g., application layer).
Advisors: Jitender S. Deogun and Dennis R. Alexande
Double Loop Interconnection Networks With Minimal Transmission Delay.
The interconnection network is a critical component in massively parallel architectures and in large communication networks. An important criterion in evaluating such networks is their transmission delay, which is determined to a large extent by the diameter of the underlying graph. The loop network is popular due to its simplicity, symmetry and expandability. By adding chords to the loop, the diameter and reliability are improved. In this work we deal with the problem of minimizing the diameter of double loop networks, which model various communication networks and also the Illiac type Mesh Connected Computer. A double loop network, (also known as circulant) G(n,h), consists of a loop of n vertices where each vertex i is also joined by chords to the vertices i h mod n. D\sbsp{\rm n}{*}, the minimal diameter of G(n,h), is bounded below by k if n R(k) = 2k\sp2 - 2k + 2,...,2k\sp2 + 2k + 1. An integer n, a hop h and a network G(n,h) are called optimal (suboptimal) if Diam G(n,h) = D\sbsp{\rm n}{*} = k (k + 1). We determine new infinite families of optimal values of n, which considerably improve previously known results. These families are of several different types and cover more than 94% of all values of n up to 8,000,000. We conjecture that all values of n are either optimal or suboptimal. Our analysis leads to the construction of an algorithm that detects optimal and suboptimal values of n. When run on a SUN workstation, it confirmed our conjecture within 60 minutes, for all values of n up to 8,000,000. Optimal (suboptimal) hops, corresponding to optimal (suboptimal) values of n, are provided by a simple construction
NASA SERC 1990 Symposium on VLSI Design
This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools
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Extremal Directed And Mixed Graphs
We consider three problems in extremal graph theory, namely the degree/diameter problem, the degree/geodecity problem and Tur\'{a}n problems, in the context of directed and partially directed graphs.
A directed graph or mixed graph is -geodetic if there is no pair of vertices of such that there exist distinct non-backtracking walks with length in from to . The order of a -geodetic digraph with minimum out-degree is bounded below by the \emph{directed Moore bound} ; similarly the order of a -geodetic mixed graph with minimum undirected degree and minimum directed out-degree is bounded below by the \emph{mixed Moore bound}. We will be interested in networks with order exceeding the Moore bound by some small \emph{excess} .
The \emph{degree/geodecity problem} asks for the smallest possible order of a -geodetic digraph or mixed graph with given degree parameters. We prove the existence of extremal graphs, which we call \emph{geodetic cages}, and provide some bounds on their order and information on their structure.
We discuss the structure of digraphs with excess one and rule out the existence of certain digraphs with excess one. We then classify all digraphs with out-degree two and excess two, as well as all diregular digraphs with out-degree two and excess three. We also present the first known non-trivial examples of geodetic cages.
We then generalise this work to the setting of mixed graphs. First we address the question of the total regularity of mixed graphs with order close to the Moore bound and prove bounds on the order of mixed graphs that are not totally regular. In particular using spectral methods we prove a conjecture of L\'{o}pez and Miret that mixed graphs with diameter two and order one less than the Moore bound are totally regular.
Using counting arguments we then provide strong bounds on the order of totally regular -geodetic mixed graphs and use these results to derive new extremal mixed graphs.
Finally we change our focus and study the Tur\'{a}n problem of the largest possible size of a -geodetic digraph with given order. We solve this problem and also prove an exact expression for the restricted problem of the largest possible size of strongly connected -geodetic digraphs, as well as providing constructions of strongly connected -geodetic digraphs that we conjecture to be extremal for larger . We close with a discussion of some related generalised Tur\'{a}n problems for -geodetic digraphs