Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

International audienceThe extensive growth of wireless communications industry is creating a big market opportunity. Wireless operators are currently searching for new solutions which would be implemented into the existing wireless communication networks to provide the broader bandwidth, the better quality and new value-added services. In the last decade, most commercial efforts were focused on the 1-10 GHz spectrum for voice and data applications for mobile phones and portable computers (Niknejad & Hashemi, 2008). Nowadays, the interest is growing in applications that use high rate wireless communications. Multigigabit- per-second communication requires a very large bandwidth. The Ultra-Wide Band (UWB) technology was basically used for this issue. However, this technology has some shortcomings including problems with interference and a limited data rate. Furthermore, the 3-5 GHz spectrum is relatively crowded with many interferers appearing in the WiFi bands (Niknejad & Hashemi, 2008). The use of millimeter wave frequency band is considered the most promising technology for broadband wireless. In 2001, the Federal Communications Commission (FCC) released a set of rules governing the use of spectrum between 57 and 66 GHz (Baldwin, 2007). Hence, a large bandwidth coupled with high allowable transmit power equals high possible data rates. Traditionally the implementation of 60 GHz radio technology required expensive technologies based on III-V compound semiconductors such as InP and GaAs (Smulders et al., 2007). The rapid progress of CMOS technology has enabled its application in millimeter wave applications. Currently, the transistors became small enough, consequently fast enough. As a result, the CMOS technology has become one of the most attractive choices in implementing 60 GHz radio due to its low cost and high level of integration (Doan et al., 2005). Despite the advantages of CMOS technology, the design of 60 GHz CMOS transceiver exhibits several challenges and difficulties that the designers must overcome. This chapter aims to explore the potential of the 60 GHz band in the use for emergent generation multi-gigabit wireless applications. The chapter presents a quick overview of the state-of-the-art of 60 GHz radio technology and its potentials to provide for high data rate and short range wireless communications. The chapter is organized as follows. Section 2 presents an overview about 60 GHz band. The advantages are presented to highlight the performance characteristics of this band. The opportunities of the physical layer of the IEEE 802.15.3c standard for emerging WPAN applications are discussed in section 3. The tremendous opportunities available with CMOS technology in the design of 60 GHz radio is discussed in section 4. Section 5 shows an example of 60 GHz radio system link. Some challenges and trade-offs on the design issues of circuits and systems for 60 GHz band are reported in section 6. Finally, section 7 presents the conclusion and some perspectives on future directions

A 5G mm-wave compact voltage-controlled oscillator in 0.25 µm pHEMT technology

A 5G mm-wave monolithic microwave integrated circuit (MMIC) voltage-controlled oscillator (VCO) is presented in this paper. It is designed on GaAs substrate and with 0.25 µm-pHEMT technology from UMS foundry and it is based on pHEMT varactors in order to achieve a very small chip size. A 0dBm-output power over the entire tuning range from 27.67 GHz to 28.91 GHz, a phase noise of -96.274 dBc/Hz and -116.24 dBc/Hz at 1 and 10 MHz offset frequency from the carrier respectively are obtained on simulation. A power consumption of 111 mW is obtained for a chip size of 0.268 mm2. According to our knowledge, this circuit occupies the smallest surface area compared to pHEMTs oscillators published in the literature

Optoelectronic oscillator for 5G wireless networks and beyond

With the development of 5G wireless network and beyond, the wireless carrier frequency will definitely reach millimeter-wave (mm-wave) and even terahertz (THz). As one of the key elements in wireless networks, the local oscillator (LO) needs to operate at mm-wave and THz band with lower phase noise, which becomes a major challenge for commercial LOs. In this article, we investigate the recent developments of the electronic integrated circuit (EIC) oscillator and the optoelectronic oscillator (OEO), and especially investigate the prospect of OEO serving as a qualified LO in the 5G wireless network and beyond. Both the EIC oscillators and OEOs are investigated, including their basic theories of operation, representative techniques and some milestones in applications. Then, we compare the performances between the EIC oscillators and the OEOs in terms of frequency accuracy, phase noise, power consumption and cost. After describing the specific requirements of LO based on the standard of 5G and 6G wireless communication systems, we introduce an injection-locked OEO architecture which can be implemented to distribute and synchronize LOs. The OEO has better phase noise performance at high frequency, which is greatly desired for LO in 5G wireless network and beyond. Besides, the OEO provides an easy and low-loss method to distribute and synchronize mm-wave and THz LOs. Thanks to photonic integrated circuit development, the power consumption and cost of OEO reduce gradually. It is foreseeable that the integrated OEO with lower cost may have a promising prospect in the 5G wireless network and beyond

The Design and Linearization of 60GHz Injection Locked Power Amplifier

The RF power amplifier is one of the most critical blocks of transceivers, as it is expected to provide a suitable output power with high gain, efficiency and linearity. In this paper, a 60-GHz power amplifier based on an injection locked structure is demonstrated in a standard 65 CMOS technology. The PA core consists of a cross-coupled pair of NMOS transistors with an NMOS current source. This structure can achieve large output power and high PAE, but with poor linearity performance. In order to improve the linearity, several linearization techniques are investigated, including adaptive biasing and predistortion. The results show that the adaptive biasing technique can enlarge the linear operation region, but results in poor AM-PM performance. By instead using the predistortion technique, the AM-PM performance can be improved, but the linear region only extends slightly. Considering theses two techniques different advantages, we combine them together to improve not only the linear region but also the AM-PM performance. Finally, a common source amplifier is added as the first stage. With proper bias, the linear operation region is then effectively extended by 7.3 dB. This two stage power amplifier achieves large output power, high linearity and high PAE simultaneously. It delivers a gain of 20dB, a Psat of 16.3dBm, a P1dB of 15.41dBm, and a PAE of 30%.Since the invention of radio-frequency (RF) wireless communication more than 100 years ago, mobile phones and other wireless communications products for civilian consumption have developed rapidly. Nowadays, the demand for larger high data rate and capacities is rising sharply. The traditional wireless bandwidth is no longer able to meet some high-rate applications requirement. However, 60GHz wireless communication system is our solution, and up to 7 GHz unlicensed wide band around 60GHz is open to use across much of the world. Furthermore, the power amplifier (PA) is a critical part of any transmitter to convert the signal to higher power and drive the antenna. For power amplifiers, efficiency and linearity are most important. Power amplifiers with low efficiency will result in high level of heat dissipation. Linearity is a measure of the signal distortion, which consists of gain compression (AM-AM distortion) and phase distortion (AM-PM distortion). In this thesis work, an injection locked power amplifier is used to reduce the input driving requirements and improve the efficiency. Simulations have been performed for implementation in 65nm standard CMOS, which is a low-cost technology for fabrication of integrated circuits (chips). The injection locked technique means that a self-oscillating circuit is forced to run at the same frequency as the input signal. Furthermore, an integrated balun is added to transfer between single-ended and differential signals. The results show that this PA can achieve high efficiency but with poor linearity performance. In order to improve the linearity, different linearization techniques are investigated, including adaptive biasing and predistortion. Adaptive biasing is a feedback technique. At high output levels, the power amplifier has less gain, which leads to signal distortion. The adaptive biasing unit can sense the output power in real time and adjust the bias. The bias is then increased at increased output power in order to restore the power gain at high output levels. Predistortion is another linearization technique. A predistorter, which has a gain expansion characteristic, is then introduced before the PA to compensate for its gain reduction. Then, considering the advantages of these two linearization techniques, we combine them together to achieve even better results. Finally, a two-stage power amplifier is proposed by adding a common source amplifier as the first stage. The first stage can also produce a gain boost at the high output levels, and this expansion gain can be made to match the second-stage gain reduction very well. The simulation results show that the amplifier can achieve high linearity and efficiency at the same time

The Performance of an Integrated Transformer in a DC/DC Converter

The separation between the low-voltage part and high-voltage part of the converter is formed by a transformer that transfers power while jamming the DC ring. The resonant mode power oscillator is utilized to allow elevated competence power transfer. The on-chip transformer is probable to have elevated value inductance, elevated quality factors and elevated coupling coefficient to decrease the loss in the oscillation. The performance of a transformer is extremely dependent on the structure, topology and other essential structures that create it compatible with the integrated circuits IC process such as patterned ground shield (PGS). Different types of transformers are modeled and simulated in MATLAB; the performances are compared to select the optimum design. The on-chip transformer model is simulated and the Results of MATLAB simulation are exposed, showing an excellent agreement in radio frequency RF

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Quadrature Frequency Synthesis for Wideband Wireless Transceivers

University of Minnesota Ph.D. dissertation. May 2014. Major: Electrical Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xi, 112 pages.In this thesis, three different techniques pertinent to quadrature LO generation in high data rate and wideband RF transceivers are presented. Prototype designs are made to verify the performance of the proposed techniques, in three different technologies: IBM 130nm CMOS process, TSMC 65nm CMOS process and IBM 32nm SOI process. The three prototype designs also cover three different frequency bands, ranging from 5GHz to 74GHz. First, an LO generation scheme for a 21 GHz center-frequency, 4-GHz instantaneous bandwidth channelized receiver is presented. A single 1.33 GHz reference source is used to simultaneously generate 20 GHz and 22 GHz LOs with quadrature outputs. Injection locking is used instead of conventional PLL techniques allowing low-power quadrature generation. A harmonic-rich signal, containing both even and odd harmonics of the input reference signal, is generated using a digital pulse slimmer. Two ILO chains are used to lock on to the 10th and 11th harmonics of the reference signal generating the 20 GHz and the 22 GHz quadrature LOs respectively. The prototype design is implemented in IBM's 130 nm CMOS process, draws 110 mA from a 1.2 V supply and occupies an active area of 1.8 square-mm. Next, a wide-tuning range QVCO with a novel complimentary-coupling technique is presented. By using PMOS transistors for coupling two VCOs with NMOS gm-cells, it is shown that significant phase-noise improvement (7-9 dB) can be achieved over the traditional NMOS coupling. This breaks the trade-off between quadrature accuracy and phase-noise, allowing reasonable accuracy without a significant phase-noise hit. The proposed technique is frequency-insensitive, allowing robust coupling over a wide tuning range. A prototype design is done in TSMC 65nm process, with 4-bits of discrete tuning spanning the frequency range 4.6-7.8 GHz (52% FTR) while achieving a minimum FOM of 181.4dBc/Hz and a minimum FOMT of 196dBc/Hz. Finally, a wide tuning-range millimeter wave QVCO is presented that employs a modified transformer-based super-harmonic coupling technique. Using the proposed technique, together with custom-designed inductors and metal capacitors, a prototype is designed in IBM 32nm SOI technology with 6-bits of discrete tuning using switched capacitors. Full EM-extracted simulations show a tuning range of 53.84GHz to 73.59GHz, with an FOM of 173 dBc/Hz and an FOMT of 183 dBc/Hz. With 19.75GHz of tuning range around a 63.7GHz center frequency, the simulated FTR is 31%, surpassing all similar designs in the same band. A slight modification in the tank inductors would enable the QVCO to be employed in multiple mm-Wave bands (57-66 GHz communication band, 71-76 GHz E-band, and 76-77 GHz radar band)