Lock-Based cache coherence protocol for chip multiprocessors

Chip multiprocessor (CMP) is replacing the superscalar processor due to its huge performance gains in terms of processor speed, scalability, power consumption and economical design. Since the CMP consists of multiple processor cores on a single chip usually with share cache resources, process synchronization is an important issue that needs to be dealt with. Synchronization is usually done by the operating system in case of shared memory multiprocessors (SMP). This work studies the effect of performing synchronization by the hardware through its integration with the cache coherence protocol. A novel cache coherence protocol, called Lock-based Cache Coherence Protocol (LCCP) was designed and its performance was compared with MESI cache coherence protocol. Experiments were performed by a functional multiprocessor simulator, MP_Simplesim, that was modified to do this work. A novel interconnection network was also designed and tested in terms of performance against the traditional bus approach by means of simulation

Token bus interconnection network for tightly-coupled multiprocessor systems

The end product of this research is the development of an efficient method of interconnecting hundreds of processors via buses that use techniques known in local area network systems. The buses provide a high bandwidth channel with a token bus protocol that significantly reduces the latency found in most interconnection systems. The system consists of a bus interface unit to provide an interface between each processor and the buses. The system provides multiple buses to increase the system throughput and reliability. The token bus protocol is based on the IEEE 802.4 protocol with modifications to facilitate the use of multiple buses;The dissertation describes the interconnection network and the performance of the network. The bus interface unit and the token bus protocol are defined. The network supports two types of media. Both are described and a comparison is made between them. The performance of the token bus protocol is studied and compared with other protocols;The interconnection network is compared with several other interconnection networks using both cost and performance measures. The token bus interconnection network shows better performance and higher network quality than the other networks

Parallel network protocol stacks using replication

Computing applications demand good performance from networking systems. This includes high-bandwidth communication using protocols with sophisticated features such as ordering, reliability, and congestion control. Much of this protocol processing occurs in software, both on desktop systems and servers. Multi-processing is a requirement on today\u27s computer architectures because their design does not allow for increased processor frequencies. At the same time, network bandwidths continue to increase. In order to meet application demand for throughput, protocol processing must be parallel to leverage the full capabilities of multi-processor or multi-core systems. Existing parallelization strategies have performance difficulties that limit their scalability and their application to single, high-speed data streams. This dissertation introduces a new approach to parallelizing network protocol processing without the need for locks or for global state. Rather than maintain global states, each processor maintains its own copy of protocol state. Therefore, updates are local and don\u27t require fine-grained locks or explicit synchronization. State management work is replicated, but logically independent work is parallelized. Along with the approach, this dissertation describes Dominoes, a new framework for implementing replicated processing systems. Dominoes organizes the state information into Domains and the communication into Channels. These two abstractions provide a powerful, but flexible model for testing the replication approach. This dissertation uses Dominoes to build a replicated network protocol system. The performance of common protocols, such as TCP/IP, is increased by multiprocessing single connections. On commodity hardware, throughput increases between 15-300% depending on the type of communication. Most gains are possible when communicating with unmodified peer implementations, such as Linux. In addition to quantitative results, protocol behavior is studied as it relates to the replication approach

A Host Interface Architecture and Implementation for ATM Networks

The advent of high speed networks has increased demands on processor architectures. These architectural demands are due to the increase in network bandwidth relative to the speeds of processor components. One important component for a high-performance system is the workstation-to-network host interface . The solution presented in this thesis migrates a carefully selected set of protocol processing functions into hardware. The host interface is highly parallel and all per cell functions are performed by dedicated logic to maximize performance. There is a clean separation between the interface functions, such as segmentation and reassembly, and the interface/host communication. This architecture has been realized in a prototype which connects an IBM RISC System/6000 workstation to a SONET-based ATM network carrying data at the OC-3c1 rate of 155 Mbps

QOS Reliability and Improvement for Congestion Probability Routing in ATM Networks

The other primitives for switch management and control are borrowed heavily from the specified protocol. They include priority for switch configuration port and switch management VP management and permanent measurement. The protocol was implemented and integrated with the OPNET platform. Without going into specifies of the protocol we describe its design principles and show how it has affected in the protocol. Traditional connection switches include an embedded processor that implements both the switch control and network signaling. The objective of CAC is to keep the network load moderate to achieve a performance objective associated with QOS. Cell loss ratio a key QOS parameter in ATM networks is essential for proper network resources dimensioning, congestion control , bandwidth allocation and routing. Keywords: Quality of Service, Servicing Monitoring

New Architecture for EIA-709.1 Protocol Implementation

This paper proposes a new architecture for EIA-709.1protocol implementation. The protocol is conventionallyimplemented with the proprietary processor and language,Neuron chip and Neuron C, respectively, where the Neuron chipconsists of 3 processors inside. The proposed architecture usesonly one general purpose processor and general ANSI C toimplement the layers of EIA-709.1 except the physical layer. Thedata link, network, and other layers are implemented onto oneRISC processor, ARM. Specifically, the data link layer of theEIA-709.1 based on predictive p-persistent CSMA/CA isimplemented. The interface between the transceiver based onpower line communication and the data link layer based on theARM is described. As a conclusion, this research shows theimprovement of performance and the compatibility with theexisting Neuron chip

tCHARM : distributed concurrent processing using multithreading

CHARM is a parallel programming language that was originally implemented for a network of workstations each of which has only one processor. In this project, we ported CHARM for a network of workstations each of which has more than one processor (multi-computer) using multithreading to exploit the multiple processors. Network performance is another issue addressed in the project. Since the messaging protocol called Fast Messages over Myrinet offers low latency and high bandwidth, we ported the messaging protocol from the original TCP/IP to Fast Messages over Myrinet