Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches

Multi-Granular Optical Cross-Connect: Design, Analysis, and Demonstration

A fundamental issue in all-optical switching is to offer efficient and cost-effective transport services for a wide range of bandwidth granularities. This paper presents multi-granular optical cross-connect (MG-OXC) architectures that combine slow (ms regime) and fast (ns regime) switch elements, in order to support optical circuit switching (OCS), optical burst switching (OBS), and even optical packet switching (OPS). The MG-OXC architectures are designed to provide a cost-effective approach, while offering the flexibility and reconfigurability to deal with dynamic requirements of different applications. All proposed MG-OXC designs are analyzed and compared in terms of dimensionality, flexibility/reconfigurability, and scalability. Furthermore, node level simulations are conducted to evaluate the performance of MG-OXCs under different traffic regimes. Finally, the feasibility of the proposed architectures is demonstrated on an application-aware, multi-bit-rate (10 and 40 Gbps), end-to-end OBS testbed

Multistage Switching Architectures for Software Routers

Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single software routers, ii) scale router size, iii) distribute packet manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize,scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under wa

Magnetic Cellular Nonlinear Network with Spin Wave Bus for Image Processing

We describe and analyze a cellular nonlinear network based on magnetic nanostructures for image processing. The network consists of magneto-electric cells integrated onto a common ferromagnetic film - spin wave bus. The magneto-electric cell is an artificial two-phase multiferroic structure comprising piezoelectric and ferromagnetic materials. A bit of information is assigned to the cell's magnetic polarization, which can be controlled by the applied voltage. The information exchange among the cells is via the spin waves propagating in the spin wave bus. Each cell changes its state as a combined effect of two: the magneto-electric coupling and the interaction with the spin waves. The distinct feature of the network with spin wave bus is the ability to control the inter-cell communication by an external global parameter - magnetic field. The latter makes possible to realize different image processing functions on the same template without rewiring or reconfiguration. We present the results of numerical simulations illustrating image filtering, erosion, dilation, horizontal and vertical line detection, inversion and edge detection accomplished on one template by the proper choice of the strength and direction of the external magnetic field. We also present numerical assets on the major network parameters such as cell density, power dissipation and functional throughput, and compare them with the parameters projected for other nano-architectures such as CMOL-CrossNet, Quantum Dot Cellular Automata, and Quantum Dot Image Processor. Potentially, the utilization of spin waves phenomena at the nanometer scale may provide a route to low-power consuming and functional logic circuits for special task data processing

The artificial retina processor for track reconstruction at the LHC crossing rate

We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large Hadron Collider events at the full crossing frequency.Comment: 4th draft of WIT proceedings modified according to JINST referee's comments. 10 pages, 6 figures, 2 table

Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (Asynchronous Transfer Mode). ATM can be characterized by very high speed transmission links and simple, hard wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks.A number of designs has been proposed for implementing ATM switches. While many differences exist among the proposals, the vast majority of them is based on self-routing multi-stage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routing capability and suitability for VLSI implementation.Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques has also been proposed to improve the performance of blocking and nonblocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues

Experimental demonstration of an ultra-low latency control plane for optical packet switching in data center networks

Optical interconnection networks have the potential to reduce latency and power consumption while increasing the bisection bandwidth of data center networks compared to electrical network architectures. Optical circuit-switched networking has been proposed but it is reconfigurable in milliseconds. Although switches operating on nanosecond timescales have been demonstrated, centrally scheduling such switching architectures is considered to be of high complexity, incurring significant delay penalties on the total switching latency. In this paper we present a high-speed control plane design based on a central switch scheduler for nanosecond optical switching which significantly reduces the end-to-end latency in the network compared to using the best electronic switches. We discuss the implementation of our control plane on field-programmable gate array (FPGA) boards and quantify its delay components. We focus on the output-port allocation circuit design which limits the scheduling delay and the end-to-end latency. Using our FPGA-implemented control plane, for a 32 × 32 switch, we experimentally demonstrate rack-scale optical packet switching with a minimum end-to-end head-to-tail latency of 71.0 ns, outperforming current state-of-the-art electronic switches. The effect of asynchronous control plane operation on the switch performance is evaluated experimentally. Finally, a new parallel allocation circuit design is presented decreasing the scheduling delay by 42.7% and the minimum end-to-end latency to 54.6 ns. More importantly, it enables scaling to a switch double the size (64 × 64) with a minimum end-to-end latency less than 71.0 ns. In a developed cycle-accurate network emulator we demonstrate nanosecond switching up to 60% of port capacity and average end-to-end latency less than 10 μs at full capacity while maintaining zero packet loss across all traffic loads