A Reduced Complexity Ungerboeck Receiver for Quantized Wideband Massive SC-MIMO

Employing low resolution analog-to-digital converters in massive multiple-input multiple-output (MIMO) has many advantages in terms of total power consumption, cost and feasibility of such systems. However, such advantages come together with significant challenges in channel estimation and data detection due to the severe quantization noise present. In this study, we propose a novel iterative receiver for quantized uplink single carrier MIMO (SC-MIMO) utilizing an efficient message passing algorithm based on the Bussgang decomposition and Ungerboeck factorization, which avoids the use of a complex whitening filter. A reduced state sequence estimator with bidirectional decision feedback is also derived, achieving remarkable complexity reduction compared to the existing receivers for quantized SC-MIMO in the literature, without any requirement on the sparsity of the transmission channel. Moreover, the linear minimum mean-square-error (LMMSE) channel estimator for SC-MIMO under frequency-selective channel, which do not require any cyclic-prefix overhead, is also derived. We observe that the proposed receiver has significant performance gains with respect to the existing receivers in the literature under imperfect channel state information.Comment: This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

Digital and Mixed Domain Hardware Reduction Algorithms and Implementations for Massive MIMO

Emerging 5G and 6G based wireless communications systems largely rely on multiple-input-multiple-output (MIMO) systems to reduce inherently extensive path losses, facilitate high data rates, and high spatial diversity. Massive MIMO systems used in mmWave and sub-THz applications consists of hundreds perhaps thousands of antenna elements at base stations. Digital beamforming techniques provide the highest flexibility and better degrees of freedom for phased antenna arrays as compared to its analog and hybrid alternatives but has the highest hardware complexity. Conventional digital beamformers at the receiver require a dedicated analog to digital converter (ADC) for every antenna element, leading to ADCs for elements. The number of ADCs is the key deterministic factor for the power consumption of an antenna array system. The digital hardware consists of fast Fourier transform (FFT) cores with a multiplier complexity of (N log2N) for an element system to generate multiple beams. It is required to reduce the mixed and digital hardware complexities in MIMO systems to reduce the cost and the power consumption, while maintaining high performance. The well-known concept has been in use for ADCs to achieve reduced complexities. An extension of the architecture to multi-dimensional domain is explored in this dissertation to implement a single port ADC to replace ADCs in an element system, using the correlation of received signals in the spatial domain. This concept has applications in conventional uniform linear arrays (ULAs) as well as in focal plane array (FPA) receivers. Our analysis has shown that sparsity in the spatio-temporal frequency domain can be exploited to reduce the number of ADCs from N to where . By using the limited field of view of practical antennas, multiple sub-arrays are combined without interferences to achieve a factor of K increment in the information carrying capacity of the ADC systems. Applications of this concept include ULAs and rectangular array systems. Experimental verifications were done for a element, 1.8 - 2.1 GHz wideband array system to sample using ADCs. This dissertation proposes that frequency division multiplexing (FDM) receiver outputs at an intermediate frequency (IF) can pack multiple (M) narrowband channels with a guard band to avoid interferences. The combined output is then sampled using a single wideband ADC and baseband channels are retrieved in the digital domain. Measurement results were obtained by employing a element, 28 GHz antenna array system to combine channels together to achieve a 75% reduction of ADC requirement. Implementation of FFT cores in the digital domain is not always exact because of the finite precision. Therefore, this dissertation explores the possibility of approximating the discrete Fourier transform (DFT) matrix to achieve reduced hardware complexities at an allowable cost of accuracy. A point approximate DFT (ADFT) core was implemented on digital hardware using radix-32 to achieve savings in cost, size, weight and power (C-SWaP) and synthesized for ASIC at 45-nm technology