Power analysis with variable traffic loads for next generation interconnection networks

Power consumption is the most important factor for the consideration of next generation supercomputers. In addition, the requirement of power usages can be even scaled up to more than 300MW (which is nearly equal to the one nuclear power plant) with the conventional networks. On the other hand, hierarchical interconnection networks can be a possible solution to those issues. 3D-TTN is a hierarchical interconnection network where lowest level is configured as the 3Dtorus network, following the 2Dtorus network at the higher-level networks. The main focus for this paper is the power analysis with variable traffic load along with the fault tolerance, cost, packing density and message traffic density of 3D-TTN comparing against various other networks. In our early research, 3D-TTN has achieved near about 21% better diameter performance, 12% better average distance performance and eventually required about 32.48% less router power usage at the lowest level than the 5Dtorus network for 1% traffic load. This paper shows the power comparison with the router and link power rather than considering the router power only. Our analysis shows that 3DTTN will require about 39.96% less router and link power than the 5Dtorus network for 10% traffic. With 30% traffic load, 3DTTN will require about 38.42% less power than the 5Dtorus network for the on-chip network. Even considering some topological parameters, 3D-TTN could also achieve some desirable performance by comparing other networks

Mathematical modelling for TM topology under uniform and hotspot traffic patterns

Interconnection networks are introduced when dealing with the connection of a significant number of processors in massively parallel systems. TM topology is one of the latest interconnection networks to solve the deadlock problem and achieve high performance in massively parallel systems. This topology is derived from a Torus topology with removing cyclic channel dependencies. In this paper, we derive a mathematical model for TM topology under uniform and hotspot traffic patterns to compute the average delay. The average delay is formulated from the sum of the average delay of network, the average waiting time of the source node and the average degree of virtual channels. The results obtained from the mathematical model exhibit a close agreement with those predicted by simulation. In addition, sufficient simulation results are presented to revisit the TM topology performance under various traffic patterns

The static performance effect of hybrid-hierarchical interconnection by shifted completely connected network

Massively parallel computer (MPC) systems execute many operations based on internal networks called interconnection networks. The performance of these networks is affected by their topolo- gies.There are many topologies of interconnection networks for MPC systems, unfortunately, they faced many drawbacks. Expanding the size of the network degrades the performance of these topologies. That is why this current paper presents a hybrid-hierarchical interconnection network (HIN) topology by Shifted Completely Connected Network (SCCN) to circumvent the drawbacks of the existing topologies. An experimental evaluation involving the design and development of a hierarchical network was carried out. A two-dimensional higher level networks has been produced and its static network performance parameters evaluated through simulators. The �nding of the simulations has shown some good performances compared to many previous designed networks. SCCN is better than all conventional networks in terms of diameter, cost and average distance

耐故障性能を有する二次元トーラス・ネットワークの適応ルーティングアルゴリズムに関する研究

湘南工科大学201

バンク型マルチポートメモリを用いたNoCルータ回路におけるリンク間共有法に関する研究

湘南工科大学201