69 research outputs found
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A study of aspects of synchronisation and communication in certain parallel computer architectures
This paper examines methods for synchronisation and communication between tasks in highly parallel arrays of processors. The development of various methods is researched and simulation techniques are applied to specific structures, to examine their effectiveness. Two approaches to simulation are presented, in the first case a discrete event simulator is applied to task synchronisation implemented with semaphores in a close coupled environment. Secondly the concurrent programming language Occam is used to simulate a systolic configuration of processors. In this case the design is verified, through actual system construction.
Conclusions are drawn regarding the design disciplines and structure imposed by the use of these simulation techniques. A close relationship is found between the behaviour of a simulation written in Occam and the same structure constructed from multiple processors.
Further research is suggested into the subject of dataflow processors, to find suitable means for simulating such systems, prior to implementation. A type of test vehicle is proposed that would operate a dataflow processor under the control of the development system
The instruction of systolic array (ISA) and simulation of parallel algorithms
Systolic arrays have proved to be well suited for Very Large
Scale Integrated technology (VLSI) since they:
-Consist of a regular network of simple processing cells,
-Use local communication between the processing cells only,
-Exploit a maximal degree of parallelism.
However, systolic arrays have one main disadvantage compared with
other parallel computer architectures: they are special purpose
architectures only capable of executing one algorithm, e.g., a
systolic array designed for sorting cannot be used to form matrix
multiplication.
Several approaches have been made to make systolic arrays more
flexible, in order to be able to handle different problems on a
single systolic array.
In this thesis an alternative concept to a VLSI-architecture
the Soft-Systolic Simulation System (SSSS), is introduced and
developed as a working model of virtual machine with the power to
simulate hard systolic arrays and more general forms of concurrency
such as the SIMD and MIMD models of computation.
The virtual machine includes a processing element consisting of
a soft-systolic processor implemented in the virtual.machine language.
The processing element considered here was a very general element
which allows the choice of a wide range of arithmetic and logical
operators and allows the simulation of a wide class of algorithms
but in principle extra processing cells can be added making a library
and this library be tailored to individual needs.
The virtual machine chosen for this implementation is the
Instruction Systolic Array (ISA). The ISA has a number of interesting
features, firstly it has been used to simulate all SIMD algorithms
and many MIMD algorithms by a simple program transformation technique,
further, the ISA can also simulate the so-called wavefront processor
algorithms, as well as many hard systolic algorithms. The ISA removes
the need for the broadcasting of data which is a feature of SIMD
algorithms (limiting the size of the machine and its cycle time) and also presents a fairly simple communication structure for MIMD
algorithms.
The model of systolic computation developed from the VLSI
approach to systolic arrays is such that the processing surface is
fixed, as are the processing elements or cells by virtue of their
being embedded in the processing surface.
The VLSI approach therefore freezes instructions and hardware
relative to the movement of data with the virtual machine and softsystolic
programming retaining the constructions of VLSI for array
design features such as regularity, simplicity and local communication,
allowing the movement of instructions with respect to data. Data can
be frozen into the structure with instructions moving systolically.
Alternatively both the data and instructions can move systolically
around the virtual processors, (which are deemed fixed relative to
the underlying architecture).
The ISA is implemented in OCCAM programs whose execution and
output implicitly confirm the correctness of the design.
The soft-systolic preparation comprises of the usual operating
system facilities for the creation and modification of files during
the development of new programs and ISA processor elements. We allow
any concurrent high level language to be used to model the softsystolic
program. Consequently the Replicating Instruction Systolic
Array Language (RI SAL) was devised to provide a very primitive program
environment to the ISA but adequate for testing. RI SAL accepts
instructions in an assembler-like form, but is fairly permissive
about the format of statements, subject of course to syntax.
The RI SAL compiler is adopted to transform the soft-systolic
program description (RISAL) into a form suitable for the virtual
machine (simulating the algorithm) to run.
Finally we conclude that the principles mentioned here can form
the basis for a soft-systolic simulator using an orthogonally
connected mesh of processors. The wide range of algorithms which the
ISA can simulate make it suitable for a virtual simulating grid
Techniques for power system simulation using multiple processors
The thesis describes development work which was undertaken to improve the speed of a real-time power system simulator used for the development and testing of control schemes. The solution of large, highly sparse matrices was targeted because this is the most time-consuming part of the current simulator. Major improvements in the speed of the matrix ordering phase of the solution were achieved through the development of a new ordering strategy. This was thoroughly investigated, and is shown to provide important additional improvements compared to standard ordering methods, in reducing path length and minimising potential pipeline stalls. Alterations were made to the remainder of the solution process which provided more flexibility in scheduling calculations. This was used to dramatically ease the run-time generation of efficient code, dedicated to the solution of one matrix structure, and also to reduce memory requirements. A survey of the available microprocessors was performed, which concluded that a special-purpose design could best implement the code generated at run-time, and a design was produced using a microprogrammable floating-point processor, which matched the code produced by the earlier work. A method of splitting the matrix solution onto parallel processors was investigated, and two methods of producing network splits were developed and their results compared. The best results from each method were found to agree well, with a predicted three-fold speed-up for the matrix solution of the C.E.G.B. transmission system from the use of six processors. This gain will increase for the whole simulator. A parallel processing topology of the partitioned network and produce the necessary structures for the remainder of the solution process
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A strategy for mapping unstructured mesh computational mechanics programs onto distributed memory parallel architectures
The motivation of this thesis was to develop strategies that would enable unstructured mesh based computational mechanics codes to exploit the computational advantages offered by distributed memory parallel processors. Strategies that successfully map structured mesh codes onto parallel machines have been developed over the previous decade and used to build a toolkit for automation of the parallelisation process. Extension of the capabilities of this toolkit to include unstructured mesh codes requires new strategies to be developed.
This thesis examines the method of parallelisation by geometric domain decomposition using the single program multi data programming paradigm with explicit message passing. This technique involves splitting (decomposing) the problem definition into P parts that may be distributed over P processors in a parallel machine. Each processor runs the same program and operates only on its part of the problem. Messages passed between the processors allow data exchange to maintain consistency with the original algorithm.
The strategies developed to parallelise unstructured mesh codes should meet a number of requirements:
The algorithms are faithfully reproduced in parallel.
The code is largely unaltered in the parallel version.
The parallel efficiency is maximised.
The techniques should scale to highly parallel systems.
The parallelisation process should become automated.
Techniques and strategies that meet these requirements are developed and tested in this dissertation using a state of the art integrated computational fluid dynamics and solid mechanics code. The results presented demonstrate the importance of the problem partition in the definition of inter-processor communication and hence parallel performance.
The classical measure of partition quality based on the number of cut edges in the mesh partition can be inadequate for real parallel machines. Consideration of the topology of the parallel machine in the mesh partition is demonstrated to be a more significant factor than the number of cut edges in the achieved parallel efficiency. It is shown to be advantageous to allow an increase in the volume of communication in order to achieve an efficient mapping dominated by localised communications. The limitation to parallel performance resulting from communication startup latency is clearly revealed together with strategies to minimise the effect.
The generic application of the techniques to other unstructured mesh codes is discussed in the context of automation of the parallelisation process. Automation of parallelisation based on the developed strategies is presented as possible through the use of run time inspector loops to accurately determine the dependencies that define the necessary inter-processor communication
Exploiting parallelism in n-D convex hull algorithms
PhD ThesisThe convex hull is a problem of primary importance because of its applications in
computational geometry. A number of sequential and parallel algorithms for computing
the convex hull of a finite set of points in the lower dimensions are known. In compar-
ison, the general n-D problem is not as well understood and parallel algorithms are not
so prevalent because the 2-D and 3-D methods are not easily extended to the general
case. This thesis presents parallel algorithms for evaluating the general n- D convex hull
problem (where 2-D and 3-D are special cases) using Swart's sequential algorithm. One of
our methods combines a gift-wrapping technique with partitioning and merge algorithms
> where the original list is split into p 1 partitions followed by the computation of
the subhulls using the sequential n-D gift-wrapping method. The partial hulls are then
combined using a fanin tree. The second method computes the convex hull in parallel
by wrapping around the edges until a complete facial lattice structure of the polytope is
generated.
Several parameterised versions of the proposed algorithms have been implemented on
the shared memory and message passing architectures. In the former, performance on an
Encore Multimax using Encore Parallel Threads and the more lightweight Microthread
programming utilities are examined. In the latter, performance on a transputer based
machine using CS- Tools is discussed. We have shown that our techniques will be useful
in the construction of faster algorithms which employ the n-D convex hull algorithms as
a sub-algorithmCommonwealth Scholarship
Commission in the United Kingdo
On the synthesis and processing of high quality audio signals by parallel computers
This work concerns the application of new computer architectures to the creation and manipulation of high-quality audio bandwidth signals. The configuration of both the hardware and software in such systems falls under consideration in the three major sections which present increasing levels of algorithmic concurrency. In the first section, the programs which are described are distributed in identical copies across an array of processing elements; these programs run autonomously, generating data independently, but with control parameters peculiar to each copy: this type of concurrency is referred to as isonomic}The central section presents a structure which distributes tasks across an arbitrary network of processors; the flow of control in such a program is quasi- indeterminate, and controlled on a demand basis by the rate of completion of the slave tasks and their irregular interaction with the master. Whilst that interaction is, in principle, deterministic, it is also data-dependent; the dynamic nature of task allocation demands that no a priori knowledge of the rate of task completion be required. This type of concurrency is called dianomic? Finally, an architecture is described which will support a very high level of algorithmic concurrency. The programs which make efficient use of such a machine are designed not by considering flow of control, but by considering flow of data. Each atomic algorithmic unit is made as simple as possible, which results in the extensive distribution of a program over very many processing elements. Programs designed by considering only the optimum data exchange routes are said to exhibit systolic^ concurrency. Often neglected in the study of system design are those provisions necessary for practical implementations. It was intended to provide users with useful application programs in fulfilment of this study; the target group is electroacoustic composers, who use digital signal processing techniques in the context of musical composition. Some of the algorithms in use in this field are highly complex, often requiring a quantity of processing for each sample which exceeds that currently available even from very powerful computers. Consequently, applications tend to operate not in 'real-time' (where the output of a system responds to its input apparently instantaneously), but by the manipulation of sounds recorded digitally on a mass storage device. The first two sections adopt existing, public-domain software, and seek to increase its speed of execution significantly by parallel techniques, with the minimum compromise of functionality and ease of use. Those chosen are the general- purpose direct synthesis program CSOUND, from M.I.T., and a stand-alone phase vocoder system from the C.D.P..(^4) In each case, the desired aim is achieved: to increase speed of execution by two orders of magnitude over the systems currently in use by composers. This requires substantial restructuring of the programs, and careful consideration of the best computer architectures on which they are to run concurrently. The third section examines the rationale behind the use of computers in music, and begins with the implementation of a sophisticated electronic musical instrument capable of a degree of expression at least equal to its acoustic counterparts. It seems that the flexible control of such an instrument demands a greater computing resource than the sound synthesis part. A machine has been constructed with the intention of enabling the 'gestural capture' of performance information in real-time; the structure of this computer, which has one hundred and sixty high-performance microprocessors running in parallel, is expounded; and the systolic programming techniques required to take advantage of such an array are illustrated in the Occam programming language
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A graph theoretic approach to transputer network design for computer vision
The work in this thesis is concerned with parallel architectures based on the Inmos transputer-type processors and parallelisation of some computer vision tasks chosen from low to high level.
The transputer is a microprocessor with a micro-programmed scheduler and four serial communication links. It directly supports parallel processing since several transputers can be connected through their links to co-operate on solving a problem. Also several processes can be run on the same transputer. A major issue in parallel processing is the communication overhead introduced by parallelising a given task. This overhead is not present in sequential processing and must be curbed if the implementation of a task on a parallel machine is to be successful. The interconnection network underlying the architecture of a parallel computer is therefore of the utmost importance.
Computer Vision consists of a hierarchy of tasks ranging from low-level operations dealing with large amounts of relatively simple data to high level operations handling increasingly complex structures. In this work a novel edge detector based on adaptive filtering and an edge detector operating on colour images are presented and implemented on a number of transputers. These parallel implementations together with implementations of vector quantisation, Fourier descriptors for shape discrimination, the Hough transform and the Maximum clique algorithm, offer a notable performance increase when compared with sequential implementations. However, every algorithm required the design of a specific network of transputers to take advantage of the parallelism and data dependencies inherent in each.
Consequently, attention is focused on the topology of interconnection networks. In particular, the communication requirements of computer vision algorithms as identified by the various computer vision tasks are analysed. These requirements together with graph theoretical considerations are then used to suggest a topology for large transputer networks. The latter is based on sub-graphs, with proven performance when used to implement interconnection networks, combined to form an architecture with improved performance. This architecture consists of a fixed structure supplemented with a dynamically reconfigured network. After describing this topology, a routing algorithm that conveys messages along shortest paths in the network is given and implemented. And finally, some practical issues in the use of transputers are considered and solutions proposed
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