167,366 research outputs found
Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node
An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching
Performance Evaluation of the Labelled OBS Architecture
A comparison of three different Optical Burst Switching (OBS) architectures
is made, in terms of performance criteria, control and hardware complexity,
fairness, resource utilization, and burst loss probability. Regarding burst
losses, we distinguish the losses due to burst contentions from those due to
contentions of Burst Control Packets (BCP). The simulation results show that as
a counterpart of an its additional hardware complexity, the labelled OBS
(L-OBS) is an efficient OBS architecture compared to a Conventional OBS (C-OBS)
as well as in comparison with Offset Time-Emulated OBS (E-OBS)
Fill the void: improved scheduling for optical switching
With ever-increasing demand for bandwidth, optical packet/burst switching is proposed to utilize more of the available capacity of optical networks in the future. In these packet-based switching techniques, packet contention on a single wavelength is resolved effectively by means of Fiber Delay Lines. The involved scheduling algorithms are typically designed to minimize packet loss and/or packet delay. By filling so-called voids, void-filling algorithms are known to outperform their non-void-filling counterparts. This however comes at a large computational cost as the void-filling algorithms have to keep track of beginnings and endings of all voids. This is opposed to the non-void-filling algorithms which only have to keep track of a single system state variable. We therefore propose a new type of algorithm that selectively creates voids that are larger than strictly needed, only when these will likely be filled. Results obtained by Monte Carlo simulation show that selective void creation can jointly reduce packet loss by 50% and packet delay by 18%, without imposing a high computational cost
Investigation of FACTS devices to improve power quality in distribution networks
Flexible AC transmission system (FACTS) technologies are power electronic solutions
that improve power transmission through enhanced power transfer volume and stability,
and resolve quality and reliability issues in distribution networks carrying sensitive
equipment and non-linear loads. The use of FACTS in distribution systems is still in
its infancy. Voltages and power ratings in distribution networks are at a level where
realistic FACTS devices can be deployed. Efficient power converters and therefore loss
minimisation are crucial prerequisites for deployment of FACTS devices.
This thesis investigates high power semiconductor device losses in detail. Analytical
closed form equations are developed for conduction loss in power devices as a function
of device ratings and operating conditions. These formulae have been shown to predict
losses very accurately, in line with manufacturer data. The developed formulae enable
circuit designers to quickly estimate circuit losses and determine the sensitivity of those
losses to device voltage and current ratings, and thus select the optimal semiconductor
device for a specific application.
It is shown that in the case of majority carrier devices (such as power MOSFETs), the
conduction power loss (at rated current) increases linearly in relation to the varying rated
current (at constant blocking voltage), but is a square root of the variable blocking voltage
when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT),
a similar relationship is observed for varying current, however where the blocking voltage
is altered, power losses are derived as a square root with an offset (from the origin).
Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel
converters suited to reactive power compensation in 11kV and 33kV systems. The cascade
cell converter is constructed from a series arrangement of cell modules. Two prospective
structures of cascade type converters were compared as a case study: the traditional type
which uses equal-sized cells in its chain, and a second with a ternary relationship between
its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state
conditions, with simplified models based on the switching function and using standard
circuit simulators. A detailed survey of non punch through (NPT) and punch through
(PT) IGBTs was completed for the purpose of designing the two cascaded converters.
Results show that conduction losses are dominant in both types of converters in NPT
and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to
be useful in one case (27-levels in the 33kV system). The ternary-sequence converter
produces lower losses in all other cases, and this is especially noticeable for the 81-level
converter operating in an 11kV network
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