Perpendicular Reading of Single Confined Magnetic Skyrmions

Thin-film sub-5 nm magnetic skyrmions constitute an ultimate scaling alternative for future digital data storage. Skyrmions are robust non-collinear spin-textures that can be moved and manipulated by small electrical currents. We show here an innovative technique to detect isolated nanoskyrmions with a current-perpendicular-to-plane geometry, which has immediate implications for device concepts. We explore the physics behind such a mechanism by studying the atomistic electronic structure of the magnetic quasiparticles. We investigate how the isolated skyrmion local-density-of-states which tunnels into the vacuum, when compared to the ferromagnetic background, is modified by the site-dependent spin-mixing of electronic states with different relative canting angles. Local transport properties are sensitive to this effect, as we report an atomistic conductance anisotropy of over 20% for magnetic skyrmions in Pd/Fe/Ir(111) thin-films. In single skyrmions, engineering this spin-mixing magnetoresistance possibly could be incorporated in future magnetic storage technologies

Electrical writing, deleting, reading, and moving of magnetic skyrmioniums in a racetrack device

A magnetic skyrmionium (also called 2$\pi$-skyrmion) can be understood as a skyrmion - a topologically non-trivial magnetic whirl - which is situated in the center of a second skyrmion with reversed magnetization. Here, we propose a new optoelectrical writing and deleting mechanism for skyrmioniums in thin films, as well as a reading mechanism based on the topological Hall voltage. Furthermore, we point out advantages for utilizing skyrmioniums as carriers of information in comparison to skyrmions with respect to the current-driven motion. We simulate all four constituents of an operating skyrmionium-based racetrack storage device: creation, motion, detection and deletion of bits. The existence of a skyrmionium is thereby interpreted as a '1' and its absence as a '0' bit.Comment: This is a post-peer-review, pre-copyedit version of an article published in Scientific Reports. The final authenticated version is available online at [DOI

A reversible conversion between a skyrmion and a domain-wall pair in junction geometry

A skyrmion is a topological texture in the continuum field theory. Recent experimental observation of skyrmions in chiral magnet evokes a flourish of its extensive study. Skyrmion is expected to be a key component of the next generation spintronics device called skyrmionics. On the other hand, there is a well established memory device encoded by a sequence of domain walls. A skyrmion carries a topological number, whereas a domain wall does not. Nevertheless, we show a conversion is possible between a skyrmion and a domain-wall pair by connecting wide and narrow nanowires, enabling the information transmission between skyrmion device and domain-wall device. Our results will be the basis of a hybrid device made of skyrmions and domain walls, where the encoded information in domain walls is converted into skyrmions, and then read out by converting the skyrmions back to domain walls after a functional control of the skyrmions.Comment: 8 pages, 5 figure

Experimental observation of magnetic bobbers for a new concept of magnetic solid-state memory

The use of chiral skyrmions, which are nanoscale vortex-like spin textures, as movable data bit carriers forms the basis of a recently proposed concept for magnetic solid-state memory. In this concept, skyrmions are considered to be unique localized spin textures, which are used to encode data through the quantization of different distances between identical skyrmions on a guiding nanostripe. However, the conservation of distances between highly mobile and interacting skyrmions is difficult to implement in practice. Here, we report the direct observation of another type of theoretically-predicted localized magnetic state, which is referred to as a chiral bobber (ChB), using quantitative off-axis electron holography. We show that ChBs can coexist together with skyrmions. Our results suggest a novel approach for data encoding, whereby a stream of binary data representing a sequence of ones and zeros can be encoded via a sequence of skyrmions and bobbers. The need to maintain defined distances between data bit carriers is then not required. The proposed concept of data encoding promises to expedite the realization of a new generation of magnetic solid-state memory

Design and Code Optimization for Systems with Next-generation Racetrack Memories

With the rise of computationally expensive application domains such as machine learning, genomics, and fluids simulation, the quest for performance and energy-efficient computing has gained unprecedented momentum. The significant increase in computing and memory devices in modern systems has resulted in an unsustainable surge in energy consumption, a substantial portion of which is attributed to the memory system. The scaling of conventional memory technologies and their suitability for the next-generation system is also questionable. This has led to the emergence and rise of nonvolatile memory ( NVM ) technologies. Today, in different development stages, several NVM technologies are competing for their rapid access to the market. Racetrack memory ( RTM ) is one such nonvolatile memory technology that promises SRAM -comparable latency, reduced energy consumption, and unprecedented density compared to other technologies. However, racetrack memory ( RTM ) is sequential in nature, i.e., data in an RTM cell needs to be shifted to an access port before it can be accessed. These shift operations incur performance and energy penalties. An ideal RTM , requiring at most one shift per access, can easily outperform SRAM . However, in the worst-cast shifting scenario, RTM can be an order of magnitude slower than SRAM . This thesis presents an overview of the RTM device physics, its evolution, strengths and challenges, and its application in the memory subsystem. We develop tools that allow the programmability and modeling of RTM -based systems. For shifts minimization, we propose a set of techniques including optimal, near-optimal, and evolutionary algorithms for efficient scalar and instruction placement in RTMs . For array accesses, we explore schedule and layout transformations that eliminate the longer overhead shifts in RTMs . We present an automatic compilation framework that analyzes static control flow programs and transforms the loop traversal order and memory layout to maximize accesses to consecutive RTM locations and minimize shifts. We develop a simulation framework called RTSim that models various RTM parameters and enables accurate architectural level simulation. Finally, to demonstrate the RTM potential in non-Von-Neumann in-memory computing paradigms, we exploit its device attributes to implement logic and arithmetic operations. As a concrete use-case, we implement an entire hyperdimensional computing framework in RTM to accelerate the language recognition problem. Our evaluation shows considerable performance and energy improvements compared to conventional Von-Neumann models and state-of-the-art accelerators

RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures

Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption