Performance analysis of pre-equalized multilevel partial response schemes

In order to achieve high speed on electrical interconnects, channel attenuation at high frequencies must be dealt with by proper transceiver design. In this paper we investigate finite-complexity MMSE pre-equalization under an average transmit power constraint, to compensate for channel distortion in the case of both full-response and precoded partial response signaling with L-PAM mapping, and consider the resulting error performance for symbol-by-symbol detection and sequence detection. For a representative electrical interconnect, we point out that the constellation size (2-PAM or 4-PAM), the type of signaling (full response or partial response), the detection method (symbol-by-symbol detection or sequence detection) and the number of pre-equalizer taps should be carefully selected in order to achieve satisfactory error performance at high data rates. For several scenarios, precoded duobinary 4-PAM is found to yield the best error performance for given average transmit power

High-speed equalization and transmission in electrical interconnections

The relentless growth of data traffic and increasing digital signal processing capabilities of integrated circuits (IC) are demanding ever faster chip-to-chip / chip-to-module serial electrical interconnects. As data rates increase, the signal quality after transmission over printed circuit board (PCB) interconnections is severely impaired. Frequency-dependent loss and crosstalk noise lead to a reduced eye opening, a reduced signal-to-noise ratio and an increased inter-symbol interference (ISI). This, in turn, requires the use of improved signal processing or PCB materials, in order to overcome the bandwidth (BW) limitations and to improve signal integrity. By applying an optimal combination of equalizer and receiver electronics together with BW-efficient modulation schemes, the transmission rate over serial electrical interconnections can be pushed further. At the start of this research, most industrial backplane connectors, meeting the IEEE and OIF specifications such as manufactured by e.g. FCI or TE connectivity, had operational capabilities of up to 25 Gb/s. This research was mainly performed under the IWT ShortTrack project. The goal of this research was to increase the transmission speed over electrical backplanes up to 100 Gb/s per channel for next-generation telecom systems and data centers. This requirement greatly surpassed the state-ofthe-art reported in previous publications, considering e.g. 25 Gb/s duobinary and 42.8 Gb/s PAM-4 transmission over a low-loss Megtron 6 electrical backplane using off-line processing. The successful implementation of the integrated transmitter (TX) and receiver (RX) (1) , clearly shows the feasibility of single lane interconnections beyond 80 Gb/s and opens the potential of realizing industrial 100 Gb/s links using a recent IC technology process. Besides the advancement of the state-of-the-art in the field of high-speed transceivers and backplane transmission systems, which led to several academic publications, the output of this work also attracts a lot of attention from the industry, showing the potential to commercialize the developed chipset and technologies used in this research for various applications: not only in high-speed electrical transmission links, but also in high-speed opto-electronic communications such as access, active optical cables and optical backplanes. In this dissertation, the background of this research, an overview of this work and the thesis organization are illustrated in Chapter 1. In Chapter 2, a system level analysis is presented, showing that the channel losses are limiting the transmission speed over backplanes. In order to enhance the serial data rate over backplanes and to eliminate the signal degradation, several technologies are discussed, such as signal equalization and modulation techniques. First, a prototype backplane channel, from project partner FCI, implemented with improved backplane connectors is characterized. Second, an integrated transversal filter as a feed-forward equalizer (FFE) is selected to perform the signal equalization, based on a comprehensive consideration of the backplane channel performance, equalization capabilities, implementation complexity and overall power consumption. NRZ, duobinary and PAM-4 are the three most common modulation schemes for ultra-high speed electrical backplane communication. After a system-level simulation and comparison, the duobinary format is selected due to its high BW efficiency and reasonable circuit complexity. Last, different IC technology processes are compared and the ST microelectronics BiCMOS9MW process (featuring a fT value of over 200 GHz) is selected, based on a trade-off between speed and chip cost. Meanwhile it also has a benefit for providing an integrated microstrip model, which is utilized for the delay elements of the FFE. Chapter 3 illustrates the chip design of the high-speed backplane TX, consisting of a multiplexer (MUX) and a 5-tap FFE. The 4:1 MUX combines four lower rate streams into a high-speed differential NRZ signal up to 100 Gb/s as the FFE input. The 5-tap FFE is implemented with a novel topology for improved testability, such that the FFE performance can be individually characterized, in both frequency- and time-domain, which also helps to perform the coefficient optimization of the FFE. Different configurations for the gain cell in the FFE are compared. The gilbert configuration shows most advantages, in both a good high-frequency performance and an easy way to implement positive / negative amplification. The total chip, including the MUX and the FFE, consumes 750mW from a 2.5V supply and occupies an area of 4.4mm × 1.4 mm. In Chapter 4, the TX chip is demonstrated up to 84 Gb/s. First, the FFE performance is characterized in the frequency domain, showing that the FFE is able to work up to 84 Gb/s using duobinary formats. Second, the combination of the MUX and the FFE is tested. The equalized TX outputs are captured after different channels, for both NRZ and duobinary signaling at speeds from 64 Gb/s to 84 Gb/s. Then, by applying the duobinary RX 2, a serial electrical transmission link is demonstrated across a pair of 10 cm coax cables and across a 5 cm FX-2 differential stripline. The 5-tap FFE compensates a total loss between the TX and the RX chips of about 13.5 dB at the Nyquist frequency, while the RX receives the equalized signal and decodes the duobinary signal to 4 quarter rate NRZ streams. This shows a chip-to-chip data link with a bit error rate (BER) lower than 10−11. Last, the electrical data transmission between the TX and the RX over two commercial backplanes is demonstrated. An error-free, serial duobinary transmission across a commercial Megtron 6, 11.5 inch backplane is demonstrated at 48 Gb/s, which indicates that duobinary outperforms NRZ for attaining higher speed or longer reach backplane applications. Later on, using an ExaMAX® backplane demonstrator, duobinary transmission performance is verified and the maximum allowed channel loss at 40 Gb/s transmission is explored. The eye diagram and BER measurements over a backplane channel up to 26.25 inch are performed. The results show that at 40 Gb/s, a total channel loss up to 37 dB at the Nyquist frequency allows for error-free duobinary transmission, while a total channel loss of 42 dB was overcome with a BER below 10−8. An overview of the conclusions is summarized in Chapter 5, along with some suggestions for further research in this field. (1) The duobinary receiver was developed by my colleague Timothy De Keulenaer, as described in his PhD dissertation. (2) Described in the PhD dissertation of Timothy De Keulenaer

Analysis of high capacity short reach optical links

Over the last few years, the global Internet traffic has grown exponentially due to the advent of the social networks, high definition streaming, online gaming, high performance computing and cloud services. The network is saturating, facing a challenge to provide enough capacity to such ever-demanding bandwidth expensive applications. Fiber optic communications is the only technology capable of dealing such high demands due to its advantages over the traditional electrical transmission technology. The short haul transmissions currently rely on direct detection due to low cost, low power and low complexity as compared to the coherent detection schemes. In order to increase the bit rate, several advance modulation formats are under investigation for short reach transmissions. Such links mostly use intensity modulation direct detection (IMDD) schemes providing a simple system when compared with the coherent receivers. In this thesis the performance of Multilevel Pulse Amplitude Modulation (MPAM) is studied using IMDD, providing good spectral efficiency as well as able to deal with the limited electronic devices bandwidth. MPAM can address the typical optical channel without the need to go with more complex and higher power modulation schemes. It provides a trade off between sensitivity and the complexity. So a simple communication system using MPAM is implemented using an external modulated laser transmitted over a distance of 2 km. In order to reduce the cost, single laser and single receiver technique is being adopted. The performance of the MPAM system in a bandwidth limited scenarios is studied with a possibility to use equalization techniques to improve the sensitivity. The utility of Forward Error Correction codes is also studied to improve the performance without increasing the latency. By increasing the number of bits per symbol, the system becomes more sensitive to the impairments. Moreover, the components and the connectors in the transmission system also introduces multipath interference (MPI) that is a key limitation to the use of advance modulation formats. Hence a detailed study is carried out to investigate the MPI effects. At the end, a novel idea based on reflective Mach-Zehnder modulator (MZM) is presented that reuses the modulated wavelength eliminating the need for a laser. As a consequent, the cost and power consumption specifically targeted for the optical interconnect environment is reduced. In a nutshell, the thesis provides an overview of the direct detection system targeted to the short optical links. It includes the studies related to the optical transmission systems and provides an insight of the available advance modulation formats and the detection schemes. Finally, the simulations and laboratory results are provided showing that adoption of MPAM is a viable solution that should be employed in high capacity short reach optical links

Longer Wavelength GaAs-Based VCSELs for Extended-Reach Optical Interconnects

Data centers of today are increasing in size and are built to accommodate strong traffic demands while providing sustainably by having clients sharing resources under one roof. Their massive scale puts pressure on the server network topology and has incited a need for data transmission links that are energy efficient and capable of operation at high bit rates with reach up to a few kilometers. Optical interconnects (OIs) offer large bandwidth and low attenuation at long distances, and are therefore suitable for this task. The most commonly used OIs, with 850 nm GaAs-based vertical-cavity surface-emitting lasers (VCSELs) and multi-mode fiber (MMF), have a 25 Gb/s reach that is limited to a few hundred meters. However, the fiber chromatic dispersion and attenuation that limit the OI reach can be reduced significantly by increasing the wavelength of this very same technology. The upper limit of the GaAs-based VCSEL technology, with strained InGaAs quantum wells (QWs), is about 1100 nm.With further improved OI performance, new hyperscale data center topologies can be realized and explored. This will lead to a larger number of possible solutions in traffic engineering as well as for power management. 1060 nm VCSELs could soon open up for lane rates of 100+ Gb/s over distances up to 2 km and help reach the Tb/s link speed aim of data center OI standards, in which capacity is built up mainly by employing multiple parallel lanes, increasing symbol rate by going from binary to four-level pulse amplitude modulation (PAM-4), and optimizing with electrical mitigation techniques such as digital signal processing.In this work we show that 1060 nm GaAs VCSELs are suitable light sources for long-reach OIs by first demonstrating their overall stable performance and capability of error-free data transmission up to 50 Gb/s back-to-back and 25 Gb/s over 1 km of MMF. With PAM-4, we show 100 Gb/s error-free capability over 100 m of MMF, suitable for wavelength division multiplexed OIs that can transmit data at several wavelengths from 850 to 1060 nm over the same fiber channel. We also assemble single-mode 1060 nm VCSEL and single-mode fiber links and demonstrate 50 Gb/s error-free transmission over 1 km using pre-emphasis and 40 Gb/s over 2 km without the use of any electrical mitigation techniques. These results stem from careful VCSEL design, including strained InGaAs QWs with GaAsP barriers, doped AlGaAs distributed Bragg reflectors, a short optical cavity and multiple oxide layers. In addition, we show that the fabrication of such a device poses no increase in complexity and can be realized using standard processing techniques

Optimized precoded spatio-temporal partial-response signaling over frequency-selective MIMO channels

Due to the continuous demand for higher bit rates, the management of the spatio-temporal intersymbol interference in frequency-selective multiple-input multiple-output (MIMO) channels becomes increasingly important. For single-input single-output channels, equalized precoded partial-response signaling is capable of handling a large amount of intersymbol interference, but, to date, no equalization scheme with general partial-response signaling has been presented for the frequency-selective MIMO channel. Not only does this contribution extend partial-response signaling to the MIMO channel by proposing a general spatio-temporal partial-response precoder, but it also develops a minimum mean-squared-error optimization framework in which the equalization coefficients and the spatio-temporal target response are jointly optimized. Three iterative optimization algorithms are discussed, which update (part of) a row of the target impulse response matrix in each iteration. In particular, the third algorithm reformulates this row optimization as a lattice decoding problem. Numerical simulations confirm that the general partial-response signaling clearly outperforms the traditional full-response signaling in terms of the mean squared error and the bit error rate. The third optimization algorithm has a better performance but a higher complexity, compared to the first and the second algorithm

Digital Signal Processing on FPGA for Short-Range Optical Communications Systems over Plastic Optical Fiber

Nowadays bandwidth requirements are increasing vertiginously. As new ways and concepts of how to share information emerge, new ways of how to access the web enter the market. Computers and mobile devices are only the beginning, the spectrum of web products and services such as IPTV, VoIP, on-line gaming, etc has been augmented by the possibility to share, store data, interact and work on the Cloud. The rush for bandwidth has led researchers from all over the world to enquire themselves on how to achieve higher data rates, and it is thanks to their efforts, that both long-haul and short-range communications systems have experienced a huge development during the last few years. However, as the demand for higher information throughput increases traditional short-range solutions reach their lim- its. As a result, optical solutions are now migrating from long-haul to short-range communication systems. As part of this trend, plastic optical fiber (POF) systems have arisen as promising candidates for applications where traditional glass optical fibers (GOF) are unsuitable. POF systems feature a series of characteristics that make them very suitable for the market requirements. More in detail, these systems are low cost, robust, easy to handle and to install, flexible and yet tolerant to bendings. Nonetheless, these features come at the expense of a considerable higher bandwidth limitation when compared to GOF systems. This thesis is aimed to the investigate the use of digital signal processing (DSP) algorithms to overcome the bandwidth limitation in short-range optical communications system based on POF. In particular, this dissertation presents the design and development of DSP algorithms on field programmable gate arrays (FPGAs) with the ultimate purpose of implementing a fully engineered 1Gbit/s Ethernet Media Converter capable of establishing data links over 50+ meters of PMMA-SI POF using an RC-LED as transmitte

Energy-Efficient Receiver Design for High-Speed Interconnects

High-speed interconnects are of vital importance to the operation of high-performance computing and communication systems, determining the ultimate bandwidth or data rates at which the information can be exchanged. Optical interconnects and the employment of high-order modulation formats are considered as the solutions to fulfilling the envisioned speed and power efficiency of future interconnects. One common key factor in bringing the success is the availability of energy-efficient receivers with superior sensitivity. To enhance the receiver sensitivity, improvement in the signal-to-noise ratio (SNR) of the front-end circuits, or equalization that mitigates the detrimental inter-symbol interference (ISI) is required. In this dissertation, architectural and circuit-level energy-efficient techniques serving these goals are presented. First, an avalanche photodetector (APD)-based optical receiver is described, which utilizes non-return-to-zero (NRZ) modulation and is applicable to burst-mode operation. For the purposes of improving the overall optical link energy efficiency as well as the link bandwidth, this optical receiver is designed to achieve high sensitivity and high reconfiguration speed. The high sensitivity is enabled by optimizing the SNR at the front-end through adjusting the APD responsivity via its reverse bias voltage, along with the incorporation of 2-tap feedforward equalization (FFE) and 2-tap decision feedback equalization (DFE) implemented in current-integrating fashion. The high reconfiguration speed is empowered by the proposed integrating dc and amplitude comparators, which eliminate the RC settling time constraints. The receiver circuits, excluding the APD die, are fabricated in 28-nm CMOS technology. The optical receiver achieves bit-error-rate (BER) better than 1E−12 at −16-dBm optical modulation amplitude (OMA), 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s. Second, a 4-level pulse amplitude modulation (PAM4) wireline receiver is described, which incorporates continuous time linear equalizers (CTLEs) and a 2-tap direct DFE dedicated to the compensation for the first and second post-cursor ISI. The direct DFE in a PAM4 receiver (PAM4-DFE) is made possible by the proposed CMOS track-and-regenerate slicer. This proposed slicer offers rail-to-rail digital feedback signals with significantly improved clock-to-Q delay performance. The reduced slicer delay relaxes the settling time constraint of the summer circuits and allows the stringent DFE timing constraint to be satisfied. With the availability of a direct DFE employing the proposed slicer, inductor-based bandwidth enhancement and loop-unrolling techniques, which can be power/area intensive, are not required. Fabricated in 28-nm CMOS technology, the PAM4 receiver achieves BER better than 1E−12 and 1.1-pJ/b energy efficiency at 60 Gb/s, measured over a channel with 8.2-dB loss at Nyquist frequency. Third, digital neural-network-enhanced FFEs (NN-FFEs) for PAM4 analog-to-digital converter (ADC)-based optical interconnects are described. The proposed NN-FFEs employ a custom learnable piecewise linear (PWL) activation function to tackle the nonlinearities with short memory lengths. In contrast to the conventional Volterra equalizers where multipliers are utilized to generate the nonlinear terms, the proposed NN-FFEs leverage the custom PWL activation function for nonlinear operations and reduce the required number of multipliers, thereby improving the area and power efficiencies. Applications in the optical interconnects based on micro-ring modulators (MRMs) are demonstrated with simulation results of 50-Gb/s and 100-Gb/s links adopting PAM4 signaling. The proposed NN-FFEs and the conventional Volterra equalizers are synthesized with the standard-cell libraries in a commercial 28-nm CMOS technology, and their power consumptions and performance are compared. Better than 37% lower power overhead can be achieved by employing the proposed NN-FFEs, in comparison with the Volterra equalizer that leads to similar improvement in the symbol-error-rate (SER) performance.</p

MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple- input multiple-output (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high- speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on- and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust low-complexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision- feedback equalizer (DFE). For a specific chip-to- chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10^(-12) for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width