Towards all-optical label switching nodes with multicast

Fiber optics has developed so rapidly during the last decades that it has be- come the backbone of our communication systems. Evolved from initially static single-channel point-to-point links, the current advanced optical backbone net- work consists mostly of wavelength-division multiplexed (WDM) networks with optical add/drop multiplexing nodes and optical cross-connects that can switch data in the optical domain. However, the commercially implemented optical net- work nodes are still performing optical circuit switching using wavelength routing. The dedicated use of wavelength and infrequent recon¯guration result in relatively poor bandwidth utilization. The success of electronic packet switching has inspired researchers to improve the °exibility, e±ciency, granularity and network utiliza- tion of optical networks by introducing optical packet switching using short, local optical labels for forwarding decision making at intermediate optical core network nodes, a technique that is referred to as optical label switching (OLS). Various research demonstrations on OLS systems have been reported with transparent optical packet payload forwarding based on electronic packet label processing, taking advantage of the mature technologies of electronic logical cir- cuitry. This approach requires optic-electronic-optic (OEO) conversion of the op- tical labels, a costly and power consuming procedure particularly for high-speed labels. As optical packet payload bit rate increases from gigabit per second (Gb/s) to terabit per second (Tb/s) or higher, the increased speed of the optical labels will eventually face the electronic bottleneck, so that the OEO conversion and the electronic label processing will be no longer e±cient. OLS with label processing in the optical domain, namely, all-optical label switching (AOLS), will become necessary. Di®erent AOLS techniques have been proposed in the last ¯ve years. In this thesis, AOLS node architectures based on optical time-serial label processing are presented for WDM optical packets. The unicast node architecture, where each optical packet is to be sent to only one output port of the node, has been in- vestigated and partially demonstrated in the EU IST-LASAGNE project. This thesis contributes to the multicast aspects of the AOLS nodes, where the optical packets can be forwarded to multiple or all output ports of a node. Multicast capable AOLS nodes are becoming increasingly interesting due to the exponen- tial growth of the emerging multicast Internet and modern data services such as video streaming, high de¯nition TV, multi-party online games, and enterprise ap- plications such as video conferencing and optical storage area networks. Current electronic routers implement multicast in the Internet protocol (IP) layer, which requires not only the OEO conversion of the optical packets, but also exhaus- tive routing table lookup of the globally unique IP addresses. Despite that, there has been no extensive studies on AOLS multicast nodes, technologies and tra±c performance, apart from a few proof-of-principle experimental demonstrations. In this thesis, three aspects of the multicast capable AOLS nodes are addressed: 1. Logical design of the AOLS multicast node architectures, as well as func- tional subsystems and interconnections, based on state-of-the-art literature research of the ¯eld and the subject. 2. Computer simulations of the tra±c performance of di®erent AOLS unicast and multicast node architectures, using a custom-developed AOLS simulator AOLSim. 3. Experimental demonstrations in laboratory and computer simulations using the commercially available simulator VPItransmissionMakerTM, to evaluate the physical layer performance of the required all-optical multicast technolo- gies. A few selected multi-wavelength conversion (MWC) techniques are particularly looked into. MWC is an essential subsystem of the AOLS node for realizing optical packet multicast by making multiple copies of the optical packet all-optically onto di®er- ent wavelengths channels. In this thesis, theMWC techniques based on cross-phase modulation and four-wave mixing are extensively investigated. The former tech- nique o®ers more wavelength °exibility and good conversion e±ciency, but it is only applicable to intensity modulated signals. The latter technique, on the other hand, o®ers strict transparency in data rate and modulation format, but its work- ing wavelengths are limited by the device or component used, and the conversion e±ciency is considerably lower. The proposals and results presented in this thesis show feasibility of all-optical packet switching and multicasting at line speed without any OEO conversion and electronic processing. The scalability and the costly optical components of the AOLS nodes have been so far two of the major obstacles for commercialization of the AOLS concept. This thesis also introduced a novel, scalable optical labeling concept and a label processing scheme for the AOLS multicast nodes. The pro- posed scheme makes use of the spatial positions of each label bit instead of the total absolute value of all the label bits. Thus for an n-bit label, the complexity of the label processor is determined by n instead of 2n

A scalable packetised radio astronomy imager

Includes bibliographical referencesModern radio astronomy telescopes the world over require digital back-ends. The complexity of these systems depends on many site-specific factors, including the number of antennas, beams and frequency channels and the bandwidth to be processed. With the increasing popularity for ever larger interferometric arrays, the processing requirements for these back-ends have increased significantly. While the techniques for building these back-ends are well understood, every installation typically still takes many years to develop as the instruments use highly specialised, custom hardware in order to cope with the demanding engineering requirements. Modern technology has enabled reprogrammable FPGA-based processing boards, together with packet-based switching techniques, to perform all the digital signal processing requirements of a modern radio telescope array. The various instruments used by radio telescopes are functionally very different, but the component operations remain remarkably similar and many share core functionalities. Generic processing platforms are thus able to share signal processing libraries and can acquire different personalities to perform different functions simply by reprogramming them and rerouting the data appropriately. Furthermore, Ethernet-based packet-switched networks are highly flexible and scalable, enabling the same instrument design to be scaled to larger installations simply by adding additional processing nodes and larger network switches. The ability of a packetised network to transfer data to arbitrary processing nodes, along with these nodes' reconfigurability, allows for unrestrained partitioning of designs and resource allocation. This thesis describes the design and construction of the first working radio astronomy imaging instrument hosted on Ethernet-interconnected re- programmable FPGA hardware. I attempt to establish an optimal packetised architecture for the most popular instruments with particular attention to the core array functions of correlation and beamforming. Emphasis is placed on requirements for South Africa's MeerKAT array. A demonstration system is constructed and deployed on the KAT-7 array, MeerKAT's prototype. This research promises reduced instrument development time, lower costs, improved reliability and closer collaboration between telescope design teams

Simulation of packet and cell-based communication networks

This thesis investigates, using simulation techniques, the practical aspects of implementing a novel mobility protocol on the emerging Broadband Integrated Services Digital Network standard. The increasing expansion of telecommunications networks has meant that the demand for simulation has increased rapidly in recent years; but conventional simulators are slow and developments in the communications field are outstripping the ability of sequential uni-processor simulators. Newer techniques using distributed simulation on a multi-processor network are investigated in an attempt to make a cell-level simulation of a non-trivial B.-I.S.D.N. network feasible. The current state of development of the Asynchronous Transfer Mode standard, which will be used to implement a B.-I.S.D.N., is reviewed and simulation studies of the Orwell Slotted Ring protocol were made in an attempt to devise a simpler model for use in the main simulator. The mobility protocol, which uses a footprinting technique to simplify hand- offs by distributing information about a connexion to surrounding base stations, was implemented on the simulator and found to be functional after a few 'special case' scenarios had been catered for

Investigating Performance and Reliability of Process Bus Networks for Digital Protective Relaying

To reduce the cost of complex and long copper wiring, as well as to achieve flexibility in signal communications, IEC 61850 part 9-2 proposes a process bus communication network between process level switchyard equipments, and bay level protection and control (P&C) Intelligent Electronic Devices (IEDs). After successful implementation of Ethernet networks for IEC 61850 standard part 8-1 (station bus) at several substations worldwide, major manufacturers are currently working on the development of interoperable products for the IEC 61850-9-2 based process bus. The major technical challenges for applying Ethernet networks at process level include: 1) the performance of time critical messages for protection applications; 2) impacts of process bus Ethernet networks on the reliability of substation protection systems. This work starts with the performance analysis in terms of time critical Sampled Value (SV) messages loss and/or delay over the IEC 61850-9-2 process bus networks of a typical substation. Unlike GOOSE, the SV message is not repeated several times, and therefore, there is no assurance that each SV message will be received from the process bus network at protection IEDs. Therefore, the detailed modeling of IEC 61850 based substation protection devices, communication protocols, and packet format is carried out using an industry-trusted simulation tool OPNET, to study and quantify number of SV loss and delay over the process bus. The impact of SV loss/delay on digital substation protection systems is evident, and recognized by several manufacturers. Therefore, a sample value estimation algorithm is developed in order to enhance the performance of digital substation protection functions by estimating the lost and delayed sampled values. The error of estimation is evaluated in detail considering several scenarios of power system relaying. The work is further carried out to investigate the possible impact of SV loss/delay on protection functions, and test the proposed SV estimation algorithm using the hardware setup. Therefore, a state-of-the-art process bus laboratory with the protection IEDs and merging unit playback simulator using industrial computers on the QNX hard-real-time platform, is developed for a typical IEC 61850-9-2 based process bus network. Moreover, the proposed SV estimation algorithm is implemented as a part of bus differential and transmission line distance protection IEDs, and it is tested using the developed experimental setup for various SV loss/delay scenarios and power system fault conditions. In addition to the performance analysis, this work also focuses on the reliability aspects of protection systems with process bus communication network. To study the impact of process bus communication on reliability indices of a substation protection function, the detailed reliability modeling and analysis is carried out for a typical substation layout. First of all, reliability analysis is done using Reliability Block Diagrams (RBD) considering various practical process bus architectures, as well as, time synchronization techniques. After obtaining important failure rates from the RBD, an extended Markov model is proposed to analyze the reliability indices of protection systems, such as, protection unavailability, abnormal unavailability, and loss of security. It is shown with the proposed Markov model that the implementation of sampled value estimation improves the reliability indices of a protection system

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Satellite Networks: Architectures, Applications, and Technologies

Since global satellite networks are moving to the forefront in enhancing the national and global information infrastructures due to communication satellites' unique networking characteristics, a workshop was organized to assess the progress made to date and chart the future. This workshop provided the forum to assess the current state-of-the-art, identify key issues, and highlight the emerging trends in the next-generation architectures, data protocol development, communication interoperability, and applications. Presentations on overview, state-of-the-art in research, development, deployment and applications and future trends on satellite networks are assembled

Silicon Photonics for High-Performance Interconnection Networks

We assert in the course of this work that silicon photonics has the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. This work showcases that chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, enable unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of this work, we demonstrate such feasibility of waveguides, modulators, switches, and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. Furthermore, we leverage the unique properties of available silicon photonic materials to create novel silicon photonic devices, subsystems, network topologies, and architectures to enable unprecedented performance of these photonic interconnection networks and computing systems. We show that the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers. Furthermore, we explore the immense potential of all-optical functionalities implemented using parametric processing in the silicon platform, demonstrating unique methods that have the ability to revolutionize computation and communication. Silicon photonics enables new sets of opportunities that we can leverage for performance gains, as well as new sets of challenges that we must solve. Leveraging its inherent compatibility with standard fabrication techniques of the semiconductor industry, combined with its capability of dense integration with advanced microelectronics, silicon photonics also offers a clear path toward commercialization through low-cost mass-volume production. Combining empirical validations of feasibility, demonstrations of massive performance gains in large-scale systems, and the potential for commercial penetration of silicon photonics, the impact of this work will become evident in the many decades that follow

WDM cross-path switching for large-scale ATM switches.

by Jin Mai.Thesis submitted in: June 1998.Thesis (M.Phil.)--Chinese University of Hong Kong, 1999.Includes bibliographical references (leaves 62-[67]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Background and Motivation --- p.1Chapter 1.2 --- Organization of the thesis --- p.8Chapter 2 --- Principles of WDM Cross-Path Switch --- p.11Chapter 2.1 --- Principles of path scheduling --- p.11Chapter 2.2 --- Call setup and path rearrangement --- p.15Chapter 2.3 --- ABR control --- p.17Chapter 3 --- Star coupler and WDM path scheduling --- p.20Chapter 3.1 --- Star coupler and other WDM ATM switches --- p.20Chapter 3.2 --- Two schemes of implementation --- p.22Chapter 4 --- input/output modules and local routing --- p.26Chapter 4.1 --- Shared buffer memory switch --- p.26Chapter 4.2 --- local routing at input/output modules --- p.29Chapter 5 --- Multicasting --- p.32Chapter 5.1 --- Two multicasting schemes --- p.32Chapter 5.2 --- Call blocking --- p.36Chapter 6 --- Performance --- p.37Chapter 6.1 --- Introduction --- p.37Chapter 6.2 --- Switch complexity --- p.38Chapter 6.3 --- Speed up --- p.40Chapter 6.4 --- Two multicasting schemes --- p.41Chapter 7 --- Switch Model and Operation --- p.47Chapter 8 --- Conclusions --- p.50Chapter A --- Effective bandwidth and QoS guarantee --- p.52Chapter A.l --- ATM service categories and QoS parameters --- p.52Chapter A.2 --- Effective bandwidth for single source --- p.53Chapter A.2.1 --- Markovian on/off source approach --- p.54Chapter A.2.2 --- Leaky bucket regulated source --- p.55Chapter A.3 --- Effective bandwidth for multiplexed sources --- p.60Chapter A.3.1 --- Gaussian model approach --- p.60Bibliography --- p.6