1,380 research outputs found

    Asynchronous Circuit Stacking for Simplified Power Management

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    As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

    A review of advances in pixel detectors for experiments with high rate and radiation

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    The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

    Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G

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    This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27dB, a noise figure below 5dB and a power consumption of 35mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1dB compression point output power (OP1dB) of 8.2dBm. The delivered output power in the linear region can be increased up to 13.2dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9GHz, from 57GHz to 66GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters

    A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

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    Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

    Characterization of 28 nm FDSOI MOS and application to the design of a low-power 2.4 GHz LNA

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    IoT is expected to connect billions of devices all over world in the next years, and in a near future, it is expected to use LR-WPAN in a wide variety of applications. Not all the devices will require of high performance but will require of low power hungry systems since most of them will be powered with a battery. Conventional CMOS technologies cannot cover these needs even scaling it to very small regimes, which appear other problems. Hence, new technologies are emerging to cover the needs of this devices. One promising technology is the UTBB FDSOI, which achieves good performance with very good energy efficiency. This project characterizes this technology to obtain a set of parameters of interest for analog/RF design. Finally, with the help of a low-power design methodology (gm/Id approach), a design of an ULP ULV LNA is performed to check the suitability of this technology for IoT

    On the Trade-Off Between Quality Factor and Tuning Ratio in Tunable High-Frequency Capacitors

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    A benchmark of tunable and switchable devices at microwave frequencies is presented on the basis of physical limitations to show their potential for reconfigurable cellular applications. Performance limitations are outlined for each given technology focusing on the quality factor (Q) and tuning ratio (eta) as figures of merit. The state of the art in terms of these figures of merit of several tunable and switchable technologies is visualized and discussed. If the performance of these criteria is not met, the application will not be feasible. The quality factor can typically be traded off for tuning ratio. The benchmark of tunable capacitor technologies shows that transistor-switched capacitors, varactor diodes, and ferroelectric varactors perform well at 2 GHz for tuning ratios below 3, with an advantage for GaAs varactor diodes. Planar microelectromechanical capacitive switches have the potential to outperform all other technologies at tuning ratios higher than 8. Capacitors based on tunable dielectrics have the highest miniaturization potential, whereas semiconductor devices benefit from the existing manufacturing infrastructure

    The Multiple Gate Mos-Jfet

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    A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented

    A miniaturized neuroprosthesis suitable for implantation into the brain

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    This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 x 400 µm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1° C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic
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