Decomposition and encoding of finite state machines for FPGA implementation

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Low-power FSMs in FPGA: Encoding alternatives

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported this work. Additional funds have been obtained from Projects 658001 and 658004 of the Fundación General de la Universidad Autónoma de Madrid

Decomposition tool targeting FPGA architectures

The growing interest in the field of logic synthesis targeting Field Programmable Gate Arrays (FPGA) and the active research carried out by a number of research groups in the area of functional decomposition is the prime motivation for this thesis. Logic synthesis has been an area of interest in many universities all over the world. The work involves the study and implementation of techniques and methods in logic synthesis. In this work, a logic synthesis tool has been developed implementing the aspects of general and complete Decomposition method based on functional decomposition techniques [4]. The tool is aimed at producing outputs faster and more efficient than the available software. C++ Standard template library is used to develop this tool. The output of this tool is designed to be compatible with the available vendor software. The tool has been tested on MCNC benchmarks and those created keeping in mind the industry requirements

Low Power Design Techniques for Digital Logic Circuits.

With the rapid increase in the density and the size of chips and systems, area and power dissipationbecome critical concern in Very Large Scale Integrated (VLSI) circuit design. Low powerdesign techniques are essential for today's VLSI industry. The history of symbolic logic and sometypical techniques for finite state machine (FSM) logic synthesis are reviewed.The state assignment is used to optimize area and power dissipation for FSMs. Two costfunctions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to searchfor a good state assignment to minimize the cost functions. The algorithm has been implementedin C. The program can produce better results than NOVA, which is integrated into SIS by DCBerkeley, and other publications both in area and power tested by MCNC benchmarks.Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flopscan save power for digital systems significantly. Three new kinds of flip-flops, called differentialCMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valuedflip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice.Most researchers have focused on developing low-power techniques in AND/OR or NAND& NOR based circuits. The low power techniques for AND /XOR based circuits are still intheir early stage of development. To implement a complex function involving many inputs,a form of decomposition into smaller subfunctions is required such that the subfunctions fitinto the primitive elements to be used in the implementation. Best polarity based XOR gatedecomposition technique has been developed, which targets low power using Huffman algorithm.Compared to the published results, the proposed method shows considerable improvement inpower dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller(FPRM) forms. Based on polarity transformation, an algorithm is developed and implementedin C language which can find the best polarity for power and area optimization. Benchmarkexamples of up to 21 inputs run on a personal computer are given

New Approaches to Column Compatibility Checking and Column-Based Input/Output Encoding for Curtis Decompositions of Completely or Incompletely Specified Switching Functions

Cube calculus is an algebraic model used to process boolean functions. Cube calculus operations are widely used in logic optimization, logic synthesis, image processing and recognition, machine learning, and other applications which require massive logic operations. The cube calculus operations can be carried out on general-purpose computers. Since these operations can involve several levels of nested loops, this approach has poor performance. A cube calculus machine which has a special data path designed to speed up cube calculus operations is presented in this thesis. This c-qbe calculus machine can execute cube calculus operations 10 to 25 times faster than the software approach on a general-purpose computer. This thesis proposes a complete design of the Cube Calculus Machine Version II (CCM2). In this design, the CCM acts as a coprocessor of the host computer; it accepts a set of instructions that let the CCM carry out cube calculus operations. This design is mapped on a reconfigurable hardware DEC PeRLe-1 board

Research on performance enhancement for electromagnetic analysis and power analysis in cryptographic LSI

制度:新 ; 報告番号:甲3785号 ; 学位の種類:博士(工学) ; 授与年月日:2012/11/19 ; 早大学位記番号:新6161Waseda Universit

The Design of Cube Calculus Machine Using Sram-Based Fpga Reconfigurable Hardware Dec’s Perle-1 Board

Presented in this thesis are new approaches to column compatibility checking and column-based input/output encoding for Curtis decompositions of switching functions. These approaches can be used in Curtis-type functional decomposition programs for applications in several scientific disciplines. Examples of applications are: minimization of combinational and sequential logic) mapping of logic functions to programmable logic devices such as CPLDs, MPGAs, and FPGAs, data encryption, data compression, pattern recognition) and image refinement. Presently, Curtis-type functional decomposition programs are used primarily for experimental purposes due to performance, quality, and compatibility issues. However) in the past few years a renewal of interest in the area of functional decomposition has resulted in significant improvements in performance and quality of multi-level decomposition programs. The goal of this thesis is to introduce algorithms that can significantly improve the performance and quality of Curtis-type decomposition programs. In doing so, it is hoped that a Curtis-type decomposition program, complete with efficient, high quality algorithms for decomposition, will be a feasible tool for use in one or more practical applications. Various testing and analyses were performed in order to evaluate the potential of algorithms presented in this thesis for use in a high quality Curtis-type decomposition program. Testing was done using a binary input, binary output Curtis-type decomposition program MULTIS/GUD. This program was implemented here at Portland State University by the Portland Oregon Logic Optimization Group

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2