State-of-the-Art Electronic Devices Based on Graphene

Graphene can be considered as the material used for electronic devices of this century, due to its excellent physical and chemical properties, which have been studied and implemented from a theoretical basis and have allowed the development of unique and innovative applications. The need for an ongoing study of the state-of-the-art electronic devices is ultimately useful for the progress achieved so far and future project applications. To date, graphene has been used individually in composite, hybrid materials or functional materials. In this chapter, an overview of their applications in nanoelectronics, particularly with an emphasis directed to flexible electronics, is presented. The description of the advantages and properties of graphene at a level of materials science and engineering is presented, in order to spread its enormous potential. In addition, the future prospects of these applications arising from the developments made currently in the laboratory phase are examined

Proximitized Materials

Advances in scaling down heterostructures and having an improved interface quality together with atomically-thin two-dimensional materials suggest a novel approach to systematically design materials. A given material can be transformed through proximity effects whereby it acquires properties of its neighbors, for example, becoming superconducting, magnetic, topologically nontrivial, or with an enhanced spin-orbit coupling. Such proximity effects not only complement the conventional methods of designing materials by doping or functionalization, but can also overcome their various limitations. In proximitized materials it is possible to realize properties that are not present in any constituent region of the considered heterostructure. While the focus is on magnetic and spin-orbit proximity effects with their applications in spintronics, the outlined principles provide also a broader framework for employing other proximity effects to tailor materials and realize novel phenomena.Comment: Invited Review to appear in Materials Today, 28 pages, 22 figure

Enrico Fermi’s IEEE Milestone in Florence. For his Major Contribution to Semiconductor Statistics, 1924-1926

Enrico Fermi, Nobel Laureate in Physics in 1938, taught at the University of Florence just for two academic years (1924-25 and 1925-26). His research activity in these two years saw the publication of the statistics bearing his name (the two original 1926 papers by E. Fermi are reproduced in full in this book), which is at the basis of semiconductors, and hence of modern electronics. This volume is printed for the placement, at the School of Engineering in Florence, of an IEEE Milestone, within the ‘IEEE Global History Network program’, commemorating the event. The IEEE (Institute of Electrical and Electronic Engineers) is the largest professional association in the world devoted to advancing technological innovation in electrical, electronic engineering, and related fields

DESIGN, MODELING, OPTIMIZATION, AND BENCHMARKING OF INTERCONNECTS AND SCALING TECHNOLOGIES AND THEIR CIRCUIT AND SYSTEM LEVEL IMPACT

This research focuses on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of different technologies and quantifying potential performance gains on a circuit and system level. From the device side, this research looks at the scaling challenges and the future scaling drivers for conventional charge-based devices implemented at the 7nm technology node and beyond. It examines the system-level performance of stacking device logic in addition to tunneling field effect transistors (TFET) and their potential as beyond-CMOS devices. Finally, this research models and benchmarks BEOL scaling challenges and evaluates proposed technological advancements such as metal barrier scaling for copper interconnects and replacing local interconnects with ruthenium. Potential impact on performance, power, and area of these interconnect technologies is quantified for fully placed and routed circuits.Ph.D

Variability-aware architectures based on hardware redundancy for nanoscale reliable computation

During the last decades, human beings have experienced a significant enhancement in the quality of life thanks in large part to the fast evolution of Integrated Circuits (IC). This unprecedented technological race, along with its significant economic impact, has been grounded on the production of complex processing systems from highly reliable compounding devices. However, the fundamental assumption of nearly ideal devices, which has been true within the past CMOS technology generations, today seems to be coming to an end. In fact, as MOSFET technology scales into nanoscale regime it approaches to fundamental physical limits and starts experiencing higher levels of variability, performance degradation, and higher rates of manufacturing defects. On the other hand, ICs with increasing number of transistors require a decrease in the failure rate per device in order to maintain the overall chip reliability. As a result, it is becoming increasingly important today the development of circuit architectures capable of providing reliable computation while tolerating high levels of variability and defect rates. The main objective of this thesis is to analyze and propose new fault-tolerant architectures based on redundancy for future technologies. Our research is founded on the principles of redundancy established by von Neumann in the 1950s and extends them to three new dimensions: 1. Heterogeneity: Most of the works on fault-tolerant architectures based on redundancy assume homogeneous variability in the replicas like von Neumann's original work. Instead, we explore the possibilities of redundancy when heterogeneity between replicas is taken into account. In this sense, we propose compensating mechanisms that select the weighting of the redundant information to maximize the overall reliability. 2. Asynchrony: Each of the replicas of a redundant system may have associated different processing delays due to variability and degradation; especially in future nanotechnologies. If we design our system to work locally in asynchronous mode then we may consider different voting policies to deal with the redundant information. Depending on how many replicas we collect before taking a decision we can obtain different trade-off between processing delay and reliability. We propose a mechanism for providing these facilities and analyze and simulate its operation. 3. Hierarchy: Finally, we explore the possibilities of redundancy applied at different hierarchy layers of complex processing systems. We propose to distribute redundancy across the various hierarchy layers and analyze the benefits that can be obtained. Drawing on the scenario of future ICs technologies, we push the concept of redundancy to its fullest expression through the study of realistic nano-device architectures. Most of the redundant architectures considered so far do not face properly the era of Terascale Computing and the nanotechnology trends. Since von Neumann applied for the first time redundancy at electronic circuits, never until now effects as common in nanoelectronics as degradation and interconnection failures have been treated directly from the standpoint of redundancy. In this thesis we address in a comprehensive manner the reliability of digital processing systems in the upcoming technology generations

Automated Placement Of A Transistor Pair For Analogue

The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint