4,026 research outputs found
Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits
The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow
Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology
Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning
applications has increased the demand of MEMS-based digital microphones.
Mobile devices have several microphones enabling noise canceling, acoustic beamforming
and speech recognition. With the development of machine learning applications
the interest to integrate sensors with neural networks has increased.
This has driven the interest to develop digital microphones in nanometer CMOS
nodes where the microphone analog-front end and digital processing, potentially
including neural networks, is integrated on the same chip.
Traditionally, analog-to-digital converters (ADCs) in digital microphones have
been implemented using high order Sigma-Delta modulators. The most common
technique to implement these high order Sigma-Selta modulators is switchedcapacitor
CMOS circuits. Recently, to reduce power consumption and make them
more suitable for tasks that require always-on operation, such as keyword recognition,
switched-capacitor circuits have been improved using inverter-based operational
amplifier integrators. Alternatively, switched-capacitor based Sigma-
Delta modulators have been replaced by continuous time Sigma-Delta converters.
Nevertheless, in both implementations the input signal is voltage encoded
across the modulator, making the integration in smaller CMOS nodes more challenging
due to the reduced voltage supply.
An alternative technique consists on encoding the input signal on time (or
frequency) instead of voltage. This is what time-encoded converters do. Lately,
time-encoding converters have gained popularity as they are more suitable to
nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have
drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs).
VCO-ADCs can be implemented using CMOS inverter based ring oscillators
(RO) and digital circuitry. They also show noise-shaping properties.
This makes them a very interesting alternative for implementation of ADCs in
nanometer CMOS nodes. Nevertheless, two main circuit impairments are present
in VCO-ADCs, and both come from the oscillator non-idealities. The first of them
is the oscillator phase noise, that reduces the resolution of the ADC. The second
is the non-linear tuning curve of the oscillator, that results in harmonic distortion
at medium to high input amplitudes.
In this thesis we analyze the use of time encoding ADCs for MEMS microphones
with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we
study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in
sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations
for the noise transfer function (NTF) of a third order sigma-delta using a second
order filter and the NSQ are presented.
Secondly, we move our attention to the topic of RO-ADCs. We present a high
dynamic range MEMS microphone 130nm CMOS chip based on an open-loop
VCO-ADC. This dissertation shows the implementation of the analog front-end
that includes the oscillator and the MEMS interface, with a focus on achieving
low power consumption with low noise and a high dynamic range. The digital
circuitry is left to be explained by the coauthor of the chip in his dissertation. The
chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5%
at 128 dBSPL with a power consumption of 438μW.
After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement
an unsampled feedback loop around the oscillator. The objective is to reduce
distortion. Additionally phase noise mitigation is achieved. A first topology
including an operational amplifier to increase the loop gain is analyzed. The design
is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR
with an analog power consumption of 600μW. A second topology without the
operational amplifier is also analyzed. Two chips are designed with this topology.
The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto-
digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a
power consumption of 482μW. The second chip includes only the oscillator and
is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog
power consumption is 153μW.
To finish this thesis, two circuits that use an FDR with a ring oscillator are
presented. The first is a capacity-to-digital converter (CDC). The second is a filter
made with an FDR and an oscillator intended for voice activity detection tasks
(VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de
machine-learning han aumentado la demanda de micrófonos digitales basados
en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación
de ruido, el beamforming o conformación de haces y el reconocimiento
de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés
por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el
interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde
el front-end analógico y el procesamiento digital del micrófono, que puede
incluir redes neuronales, está integrado en el mismo chip.
Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos
digitales han sido implementados utilizando moduladores Sigma-Delta de
orden elevado. La técnica más común para implementar estos moduladores Sigma-
Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente,
para reducir el consumo de potencia y hacerlos más adecuados para las tareas que
requieren una operación continua, como el reconocimiento de palabras clave, los
convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con
el uso de integradores implementados con amplificadores operacionales basados
en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas
han sido reemplazados por moduladores en tiempo continuo. No obstante,
en ambas implementaciones, la señal de entrada es codificada en voltaje durante
el proceso de conversión, lo que hace que la integración en nodos CMOS más
pequeños sea complicada debido a la menor tensión de alimentación.
Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o
frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación
temporal. Recientemente, los convertidores de codificación temporal
han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos
que los convertidores Sigma-Delta. Entre los que más interés han despertado
encontramos los ADCs basados en osciladores controlados por tensión
(VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo
(RO) implementados con inversores CMOS y circuitos digitales. Esta familia
de convertidores también tiene conformado de ruido. Esto los convierte en una
alternativa muy interesante para la implementación de convertidores en nodos
CMOS nanométricos. Sin embargo, dos problemas principales están presentes en
este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero
de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no
lineal del oscilador, lo que causa distorsión a amplitudes medias y altas.
En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos
MEMS, con especial interés en ADCS basados en osciladores de anillo
(RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado
de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador
agrega un orden adicional de conformado de ruido al modulador, mejorando la
resolución. En este documento se explica el cuantificador y obtienen las ecuaciones
para la función de transferencia de ruido (NTF) de un sigma-delta de tercer
orden usando un filtro de segundo orden y el NSQ.
En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos
el chip de un micrófono MEMS de alto rango dinámico en CMOS de
130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación
del front-end analógico que incluye el oscilador y la interfaz con
el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un
bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La
descripción del back-end digital se deja para la tesis del couator del chip. La
SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD
de 1,5% a 128 dBSPL y un consumo de potencia de 438μW.
Finalmente, se analiza el uso de una resistencia dependiente de frecuencia
(FDR) para implementar un bucle de realimentación no muestreado alrededor
del oscilador. El objetivo es reducir la distorsión. Además, también se logra la
mitigación del ruido de fase del oscilador. Se analyza una primera topologia de
realimentación incluyendo un amplificador operacional para incrementar la ganancia
de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que
logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la
parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador
operacional. Se fabrican y miden dos chips diseñados con esta topologia.
El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye
el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de
76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador
y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el
el consumo de potencia analógica es de 153μW.
Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador
en anillo. El primero es un convertidor de capacidad a digital (CDC). El
segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de
detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout
High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion
The purpose of this thesis is the proposal and implementation of data conversion
open-loop architectures based on voltage-controlled oscillators (VCOs) built with
ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to
the newest complementary metal-oxide-semiconductor (CMOS) nodes.
The scaling of the design technologies into the nanometer range imposes the
reduction of the supply voltage towards small and power-efficient architectures,
leading to lower voltage overhead of the transistors. Additionally, phenomena
like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between
devices and PVT variations) make the design of classic structures for ADCs more
challenging. In recent years, time-encoded A/D conversion has gained relevant
popularity due to the possibility of being implemented with mostly digital structures.
Within this trend, VCOs designed with ring oscillator based topologies
have emerged as promising candidates for the conception of new digitization
techniques.
RO-based data converters show excellent scalability and sensitivity, apart from
some other desirable properties, such as inherent quantization noise shaping and
implicit anti-aliasing filtering. However, their nonlinearity and the limited time
delay achievable in a simple NOT gate drastically limits the resolution of the converter,
especially if we focus on wide-band A/D conversion. This thesis proposes
new ways to alleviate these issues.
Firstly, circuit-based techniques to compensate for the nonlinearity of the ring
oscillator are proposed and compared to equivalent state-of-the-art solutions.
The proposals are designed and simulated in a 65-nm CMOS node for open-loop
RO-based ADC architectures. One of the techniques is also validated experimentally
through a prototype. Secondly, new ways to artificially increase the effective
oscillation frequency are introduced and validated by simulations. Finally, new
approaches to shape the quantization noise and filter the output spectrum of a
RO-based ADC are proposed theoretically. In particular, a quadrature RO-based
band-pass ADC and a power-efficient Nyquist A/D converter are proposed and
validated by simulations.
All the techniques proposed in this work are especially devoted for highbandwidth
applications, such as Internet-of-Things (IoT) nodes or maximally
digital radio receivers. Nevertheless, their field of application is not restricted to
them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas
de conversión de datos basadas en osciladores en anillos, compatibles
con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación
más modernos donde las estructuras digitales se ven favorecidas.
La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción
de la tensión de alimentación para el desarrollo de arquitecturas pequeñas
y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión
para saturar transistores, lo que añadido a una ganancia cada vez menor
de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones
de proceso, tensión y temperatura han llevado a que sea cada vez más complejo
el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión
A/D basada en codificación temporal ha ganado gran popularidad dado
que permite la implementación de estructuras mayoritariamente digitales. Como
parte de esta evolución, los osciladores controlados por tensión diseñados con topologías
de oscilador en anillo han surgido como un candidato prometedor para
la concepción de nuevas técnicas de digitalización.
Los convertidores de datos basados en osciladores en anillo son extremadamente
sensibles (variación de frecuencia con respecto a la señal de entrada) así como
escalables, además de otras propiedades muy atractivas, como el conformado
espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su
respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta
NOT restringen la resolución del conversor, especialmente para conversión A/D
en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas
técnicas para aliviar este tipo de problemas.
En primer lugar, se proponen técnicas basadas en circuito para compensar el
efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones
equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología
CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas
presentadas es también validada experimentalmente a través de un prototipo.
En segundo lugar, se introducen y validan por simulación varias formas de incrementar
artificialmente la frecuencia de oscilación efectiva. Para finalizar, se
proponen teóricamente dos enfoques para configurar nuevas formas de conformación
del ruido de cuantificación y filtrado del espectro de salida de los datos
digitales. En particular, son propuestos y validados por simulación un ADC pasobanda
en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente
para aplicaciones de alto ancho de banda, tales como módulos para el Internet
de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar
de ello, son extrapolables también a otros campos como el de la instrumentación
biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí
FPGAs in Industrial Control Applications
The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs
Front-ends para LiDAR baseados em ADC e TDC
Autonomous vehicles are a promising technology to save over a million lives each
year that are lost in road accidents. However, bringing safe autonomous vehicles
to market requires massive development, starting with vision sensors. LiDAR is a
fundamental vision sensor for autonomous vehicles, as it enables high resolution
3D vision. However, automotive LiDAR is not yet a mature technology, and, also
requires massive development in many aspects.
This thesis aims to contribute to the maturity of LiDAR, focusing on sampling
architectures for LiDAR front-ends. Two architectures were developed.
The first is based on a pipelined ADC, available from an AD-FMCDAQ2-EBZ
board. The ADC is synchronized with the emitted pulse and able to sample
at 1 Gsample/s. The second architecture is based on a TDC that is directly
implemented in an FPGA. It relies on a tapped delay line topology comprising 45
delay elements and on a mux-based decoder, resulting in a resolution of 50 ps.
Preliminary test results show that both implementations operate correctly,
and are both suitable for sampling short pulses typically used by LiDARs. When
comparing both architectures, we conclude that an ADC consumes a significant
amount of power, and uses many FPGA resources. However, it samples the LiDAR
waveform without any loss of information, therefore enabling maximum range and
precision. The TDC is just the opposite: it consumes little power, and uses less
FPGA resources. However, it only captures one sample per pulse.Os veículos autónomos são uma tecnologia promissora para salvar mais de um
milhão de vidas por ano, colhidas por acidentes rodoviários. Contudo, colocar
veículos autónomos seguros no mercado requer inúmeros desenvolvimentos, a
começar por sensores de visão. O LiDAR é um sensor de visão fundamental para
veículos autónomos, pois permite uma visão 3D de alta resolução. Contudo, o
LiDAR automotivo não é uma tecnologia madura, e portanto requer também
desenvolvimento em vários aspectos.
Esta dissertação visa contribuir para a maturidade do LiDAR, com foco em
arquiteturas de amostragem para front-ends de LiDAR. Foram desenvolvidas duas
arquiteturas. A primeira assenta numa ADC pipelined, por sua vez implementada
numa placa de teste AD-FMCDAQ2-EBZ. A ADC opera em sincronismo com
o pulso emitido, e permite capturar amostras a 1 Gsample/s. A segunda
arquitetura assenta num TDC implementado diretamente numa FPGA. O
TDC baseia-se numa topologia tapped delay line com 45 linhas de atraso, e num
descodificador à base de multiplexers, permitindo uma resolução temporal de 50 ps.
Resultados preliminares mostram que ambas as implementações operam
corretamente, e são adequadas para amostrar pulsos curtos tipicamente associados
a LiDAR. Em termos comparativos, a arquitectura com base numa ADC tem
um consumo de potência considerável e requer uma quantidade significativa
de recursos da FPGA. Contudo, esta permite amostrar a forma de onda de
LiDAR sem nenhuma perda de informação, permitindo assim alcance e precisão
máximos. A arquitectura com base num TDC é exatamente o oposto: tem um
baixo consumo de potência e requer poucos recursos da FPGA. Contudo, permite
capturar apenas uma amostra por pulso.Mestrado em Engenharia Eletrónica e Telecomunicaçõe
Integrated Circuits and Systems for Smart Sensory Applications
Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de
imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da
matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos
de operação, assim como as suas características físicas e suas métricas de avaliação. No
seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem
atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais
do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto
com o possível trabalho futuro
Design of a Digital Temperature Sensor based on Thermal Diffusivity in a Nanoscale CMOS Technology
Temperature sensors are widely used in microprocessors to monitor on-chip temperature gradients and hot-spots, which are known to negatively impact reliability. Such sensors should be small to facilitate floor planning, fast to track millisecond thermal transients, and easy to trim to reduce the associated costs. Recently, it has been shown that thermal diffusivity (TD) sensors can meet these requirements. These sensors operate by digitalizing the temperature-dependent delay associated with the diffusion of heat pulses through an electro-thermal filter (ETF), which, in standard CMOS, can be readily implemented as a resistive heater surrounded by a thermopile. Unlike BJT-based temperature sensors, their accuracy actually improves with CMOS scaling, since it is mainly limited by the accuracy of the heather/thermopile spacing. In this work is presented the electrical design of an highly digital TD sensor in 0.13 µm CMOS with an accuracy better than 1 ºC resolution at with 1 kS/s sampling rate, and which compares favourably to state-of-the-art sensors with similar accuracy and sampling rates [1][2][3][4]. This advance is mainly enabled by the adoption of a highly digital CCO-based phasedomain ΔΣ ADC. The TD sensor presented consists of an ETF, a transconductance stage, a current-controlled oscillator (CCO) and a 6 bit digital counter. In order to be easily ported to nanoscale CMOS technologies, it is proposed to use a sigmadelta modulator based on a CCO as an alternative to traditional modulators. And since 70% of the sensor’s area is occupied by digital circuitry, porting the sensor to latest CMOS technologies process should reduce substantially the occupied die area, and thus reduce significantly the total sensor area
Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications
Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors.
Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved.
We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor.
The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor.
An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS.
Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura.
Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor.
El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión.
Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig
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