32 research outputs found

    A dynamic computation method for fast and accurate performance evaluation of multi-core architectures

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    Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models

    Towards the Performance Analysis of Apache Tez Applications

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    Apache Tez is an application framework for large data processing using interactive queries. When a Tez developer faces the ful llment of performance requirements s/he needs to con gure and optimize the Tez application to speci c execution contexts. However, these are not easy tasks, though the Apache Tez con guration will im- pact in the performance of the application signi cantly. Therefore, we propose some steps, towards the modeling and simulation of Apache Tez applications, that can help in the performance assessment of Tez designs. For the modeling, we propose a UML pro le for Apache Tez. For the simulation, we propose to transform the stereotypes of the pro le into stochastic Petri nets, which can be eventually used for computing performance metrics

    Software Architecture Description & UML Workshop

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    A Probabilistic Approach for the System-Level Design of Multi-ASIP Platforms

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