12 research outputs found
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Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)
Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology
JTEC Panel report on electronic manufacturing and packaging in Japan
This report summarizes the status of electronic manufacturing and packaging technology in Japan in comparison to that in the United States, and its impact on competition in electronic manufacturing in general. In addition to electronic manufacturing technologies, the report covers technology and manufacturing infrastructure, electronics manufacturing and assembly, quality assurance and reliability in the Japanese electronics industry, and successful product realization strategies. The panel found that Japan leads the United States in almost every electronics packaging technology. Japan clearly has achieved a strategic advantage in electronics production and process technologies. Panel members believe that Japanese competitors could be leading U.S. firms by as much as a decade in some electronics process technologies
Investigation into Solder Joint Failure in Portable Electronics Subjected to Drop Impact
Ph.DDOCTOR OF PHILOSOPH
Large-area flexible printed circuits for automotive applications
To meet the demands for safety and passenger comfort, modem passenger cars offer more
and increasingly sophisticated electrical and electronic systems. The wiring harnesses that
support such systems become too large, complex and heavy, when designed for a
conventional electrical architecture based on 14 volts, posing several challenges to
automotive manufacturers. Alternative electrical architectures based on 42 volts and in-vehicle
multiplexing promise to reduce the size and weight of the wiring harness, but these
architectures are yet to be fully developed and standardized. In the near term, alternative
wiring solutions have gained the interest of automotive manufacturers.
Small flexible printed circuits (FPCs) have previously been integrated into automotive
instrument clusters. The benefits of reduced weight and space requirements of such FPCs
compared to a wire harness has fuelled an interest in much larger FPCs as substitutes for the
Instrument Panel and door harnesses in high-volume production cars. This research
investigates the materials typically used in FPC manufacture, for applicability within a
passenger car. [Continues.
Development of the MCM-D Technique for Pixel Detector Modules
Diese Dissertation behandelt eine Kupfer-Polymer basierte
Dünnfilmtechnologie, die MCM-D Technik, und Ihre Anwendung zum
Aufbau von hybriden Pixeldetektor Modulen.
Das ATLAS Experiment am LHC wird über ein
Pixeldetektorsystem verfügen. Die kleinste mechanische Einheit
des Pixeldetektors sind Multichipmodule. Die wichtigsten
Komponenten dieser Module sind 16 Elektronikchips, ein
Kontrollchip und ein Sensor, der über mehr als 46000
Pixelzellen verfügt. MCM-D ist eine verbesserte
Technologie um das notwendigen Signalbussystem und das
Stromversorgungssystem direkt auf den Sensor aufzubauen.
In Zusammenarbeit mit dem Fraunhofer Institut für
Zuverlässigkeit und Mikrointegration, IZM, wurde der
Dünnfilmprozess überprüft und weiterentwickelt. Das
Vielschichtsystem wurde entworfen und sowohl für das
Verbindungssystem als auch für die mehr als 46000
Pixelkontakte optimiert.
Labormessungen an Prototypen haben gezeigt, dass ein
komplexes Verbindungsschema für geometrieoptimierte
Einzelchips durchführbar ist und
vernachlässigbaren Einfluss auf die Leistungsfähigkeit der
Auslesechips hat. Ein vollständiges Modul wurde gebaut; und es
wurde nachgewiesen, dass sich die Technologie eignet um
Pixeldetektormodule zu bauen. Weitere Tests beinhalten u.a. die
Untersuchung des Einflusses von hadronischer Bestrahlung auf die
Dünnfilmlagen. Einzelchipaufbauten wurden auch in einer
Teststrahlumgebung betrieben und die Umsetzbarkeit der
Sensoroptimierung konnte gezeigt werden. Es wird ein Überblick
über das Potential und die Perspektive der MCM-D Technologie
in zukünftigen Experimenten gegeben.This thesis treats a copper--polymer based thin film technology,
the MCM-D technique and its application when building hybrid
pixel detector modules.
The ATLAS experiment at the LHC will be equipped
with a pixel detector system. The basic mechanical units of the
pixel detector are multi chip modules. The main components of
these modules are: 16 electronic chips, a controller chip and a
large sensor tile, featuring more than 46000 sensor cells.
MCM-D is a superior technique to build the necessary signal bus
system and the power distribution system directly on the active
sensor tile.
In collaboration with the Fraunhofer Institute for Reliability and
Microintegration, IZM, the thin film process is reviewed
and enhanced. The multi layer system was designed and optimized
for the interconnection system as well as for the 46000 pixel
contacts. Laboratory measurements on prototypes
prove that complex routing schemes for geometrically optimized single
chips are suitable and have negligible influence on the front--end
chips performance. A full scale MCM-D module has been built and
it is shown that the technology is suitable to build pixel
detector modules. Further tests include the investigation of the
impact of hadronic irradiation on the thin film layers. Single
chip assemblies have been operated in a test beam environment and
the feasibility of the optimization of the sensors could be shown.
A review on the potential as well as the perspective for the
MCM-D technique in future experiments is given
Topical Workshop on Electronics for Particle Physics
The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities
Cost modelling and concurrent engineering for testable design
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system.
This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems.
The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented
Design Development Test and Evaluation (DDT and E) Considerations for Safe and Reliable Human Rated Spacecraft Systems
A team directed by the NASA Engineering and Safety Center (NESC) collected methodologies for how best to develop safe and reliable human rated systems and how to identify the drivers that provide the basis for assessing safety and reliability. The team also identified techniques, methodologies, and best practices to assure that NASA can develop safe and reliable human rated systems. The results are drawn from a wide variety of resources, from experts involved with the space program since its inception to the best-practices espoused in contemporary engineering doctrine. This report focuses on safety and reliability considerations and does not duplicate or update any existing references. Neither does it intend to replace existing standards and policy