Low-Dimensional Materials for Disruptive Microwave Antennas Design

This chapter is devoted to a complete analysis of remarkable electromagnetic properties of nanomaterials suitable for antenna design miniaturization. After a review of state of the art mesoscopic scale modeling tools and characterization techniques in microwave domain, new approaches based on wideband material parameters identification (complex permittivity and conductivity) will be described from impedance equivalence formulation achievement by de-embedding techniques applicable in integrated technology or in free space. A focus on performances of 1D materials such as vertically aligned multi-wall carbon nanotube (VA-MWCNT) bundles, from theory to technology, will be presented as a disruptive demonstration for defense and civil applications as in radar systems

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Technological Integration in Printed Electronics

Conventional electronics requires the use of numerous deposition techniques (e.g. chemical vapor deposition, physical vapor deposition, and photolithography) with demanding conditions like ultra-high vacuum, elevated temperature and clean room facilities. In the last decades, printed electronics (PE) has proved the use of standard printing techniques to develop electronic devices with new features such as, large area fabrication, mechanical flexibility, environmental friendliness and—potentially—cost effectiveness. This kind of devices is especially interesting for the popular concept of the Internet of Things (IoT), in which the number of employed electronic devices increases massively. Because of this trend, the cost and environmental impact are gradually becoming a substantial issue. One of the main technological barriers to overcome for PE to be a real competitor in this context, however, is the integration of these non-conventional techniques between each other and the embedding of these devices in standard electronics. This chapter summarizes the advances made in this direction, focusing on the use of different techniques in one process flow and the integration of printed electronics with conventional systems

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

The massive levels of integration following Moore\u27s Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC\u27s is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC\u27s to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator

Current transport modeling of carbon nanotube field effect transistors for analysis and design of integrated circuits

The purpose of this study was to develop a complete current transport model for carbon nanotube field effect transistors (CNT-FETs) applicable in the analysis and design of integrated circuits. The model was derived by investigating the electronic structure of carbon nanotubes and using basic laws of electrostatics describing a field effect transistor. We first derived analytical expressions for the carrier concentration in carbon nanotubes for different chiral vectors (n,m) by studying and characterizing their electronic structure. Results showed a strong relation to the diameter and wrapping angle of carbon nanotubes. The charge distribution in a CNT-FET is characterized from the charge neutrality and potential balance conditions. Mathematical techniques are used to derive analytically approximated equations describing the carbon nanotube potential in terms of the terminal voltages. These equations are validated by comparing them with the respective numerical solutions; furthermore, the expressions for the carbon nanotube potential are used to derive current transport equations for normal and subthreshold operations. Threshold and saturation voltages expressions are each derived in the process and the I-V characteristics for CNT-FETs are calculated using different combinations of chiral vectors. Results showed a strong dependence of the I-V characteristics on the wrapping angle and diameter of carbon nanotubes, as expected from the carrier concentration modeling. Results were also compared with available experimental data showing close agreement within the limitations and approximations used in the analysis. In addition, the current model equations were used to generate the voltage transfer characteristics for basic logic circuits based on complementary CNT-FETs. The voltage transfer characteristics exhibit characteristics similar to the voltage transfer characteristics of standard CMOS logic devices, with a sharp transition near the logic threshold voltage depending on the input conditions. A small-signal radio frequency (rf) model was also developed and it is shown to have cut-off frequencies in the upper GHz range with a strong dependence on the chiral vector and corresponding transconductance (gm). Finally, due to the rapid growth of carbon nanotubes as bio- and chemical sensing devices, we have also presented, using our current model equations, possible methods to interpret and analyze CNT-FETs when utilized as biosensors

Carbon nanotubes for thermal interface materials in microelectronic packaging

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ~35% and ~65%, respectively, in tensile strength (~0.8 GPa) and modulus (~90 GPa) during tensile testing; an ~20% improvement in electrical conductivity (~80000 S m⁻¹) was also reported. The mechanism of the microwave response of CNTs was discussed. Such an microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ~30 mm² s⁻¹ along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ~27 and ~540 W m⁻¹ K⁻¹, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ~1×10⁻⁷ m² K W⁻¹. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.PhDCommittee Chair: Wong, C. P.; Committee Member: Graham, Samuel; Committee Member: Hess, Dennis; Committee Member: Jacob, Karl; Committee Member: Wang, Z. L.; Committee Member: Yao, Don

Self-Healing of Open-Circuit Faults in Organic Thin-Film Transistor-Based Flexible Electronics

Flexible electronics has attracted tremendous attention due to the fast-growing market for portable devices and sensors. However, these devices usually suffer from internal and external forces, which can lead to the failure of interconnects in the circuit. To address this issue, some passive and active strategies have been developed for improving the reliability of interconnects in circuits. Although all these strategies are effective in tackling problems related to the mechanical stress, they have inherent limit in dealing with other failure causes or repairing the open fault. Therefore, in this dissertation, a particle-based self-healing (PBSH) technique has been developed. The detailed study starts with an overall review of the state of the art in techniques developed for improving the reliability of interconnects in flexible circuits. Then the mechanisms of the PBSH technique are analysed and the chemical treatment of metal particles are explored. The physical modelling of the healing is established, and relations between the healing time with the suspension concentration, electric field, length of open gap, and external resistance are verified by experimental results. In addition, to avoid the inherent conductivity of the suspension and the aggregation of micro-particles, they are modified by the oleic acid. This chemical treatment of metal particles improves the uniformity of the suspension and sets a threshold electric field for the occurrence of self-healing. As a key component in flexible circuits, an organic thin-film transistor (OTFT) fabricated by all inkjet-printing process has been developed and characterised in this study. This transistor uses 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPSPentacene) as the semiconductor, poly (vinyl cinnamate) (PVC) as the dielectric, silver as the electrodes, and CYTOP as the encapsulation. Based on this device, two basic circuits: the current mirror and the common-source (CS) amplifier have been successfully built on flexible substrates. The proper functioning of the printed devices and circuits becomes the base for the study of the self-healing in flexible circuits. Subsequently, the PBSH in OTFT device and circuit interconnects is verified. This technique can successfully repair open faults at both source and drain sides in OTFT device interconnects. Simultaneously, it can heal open faults occurring at different locations in flexible current mirror and common-source amplifier circuits biased at the static state. Moreover, the self-healing is also proved to be effective and stable in common-source amplifier when processing alternating current (AC) signals. In order to demonstrate the feasibility of the PBSH technique in real-world applications, more performance characterisations have been conducted. The bending test shows the reliability and stability of the healing in the bent condition. And the dualfaults test verifies the ability of the PBSH technique for healing more than one open fault in interconnects. In addition, methods of packaging the circuit and confining the healing material in the expected region are also developed, which prove the feasibility and manufacturability of the PBSH technique in integrated circuits. This study sets a new benchmark for improving the reliability of inkjet-printed flexible circuits

Device and circuit-level models for carbon nanotube and graphene nanoribbon transistors

Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed generation of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with integrated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density

Design and modelling of different SRAM's based on CNTFET 32nm technology

Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn't require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.Comment: 15 Page