System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

A Real-Time GPP Software-Defined Radio Testbed for the Physical Layer of Wireless Standards

We present our contribution to the general-purpose-processor-(GPP)-based radio. We describe a baseband software-defined radio testbed for the physical layer of wireless LAN standards. All physical layer functions have been successfully mapped on a Pentium 4 processor that performs these functions in real time. The testbed consists of a transmitter PC with a DAC board and a receiver PC with an ADC board. In our project, we have implemented two different types of standards on this testbed, a continuous-phase-modulation-based standard, Bluetooth, and an OFDM-based standard, HiperLAN/2. However, our testbed can easily be extended to other standards, because the only limitation in our testbed is the maximal channel bandwidth of 20 MHz and of course the processing capabilities of the used PC. The transmitter functions require at most 714 M cycles per second and the receiver functions need 1225 M cycles per second on a Pentium 4 processor. In addition, baseband experiments have been carried out successfully

MIMO-UFMC Transceiver Schemes for Millimeter Wave Wireless Communications

The UFMC modulation is among the most considered solutions for the realization of beyond-OFDM air interfaces for future wireless networks. This paper focuses on the design and analysis of an UFMC transceiver equipped with multiple antennas and operating at millimeter wave carrier frequencies. The paper provides the full mathematical model of a MIMO-UFMC transceiver, taking into account the presence of hybrid analog/digital beamformers at both ends of the communication links. Then, several detection structures are proposed, both for the case of single-packet isolated transmission, and for the case of multiple-packet continuous transmission. In the latter situation, the paper also considers the case in which no guard time among adjacent packets is inserted, trading off an increased level of interference with higher values of spectral efficiency. At the analysis stage, the several considered detection structures and transmission schemes are compared in terms of bit-error-rate, root-mean-square-error, and system throughput. The numerical results show that the proposed transceiver algorithms are effective and that the linear MMSE data detector is capable of well managing the increased interference brought by the removal of guard times among consecutive packets, thus yielding throughput gains of about 10 - 13 $\%$. The effect of phase noise at the receiver is also numerically assessed, and it is shown that the recursive implementation of the linear MMSE exhibits some degree of robustness against this disturbance

Algorithm-Architecture Co-Design for Digital Front-Ends in Mobile Receivers

The methodology behind this work has been to use the concept of algorithm-hardware co-design to achieve efficient solutions related to the digital front-end in mobile receivers. It has been shown that, by looking at algorithms and hardware architectures together, more efficient solutions can be found; i.e., efficient with respect to some design measure. In this thesis the main focus have been placed on two such parameters; first reduced complexity algorithms to lower energy consumptions at limited performance degradation, secondly to handle the increasing number of wireless standards that preferably should run on the same hardware platform. To be able to perform this task it is crucial to understand both sides of the table, i.e., both algorithms and concepts for wireless communication as well as the implications arising on the hardware architecture. It is easier to handle the high complexity by separating those disciplines in a way of layered abstraction. However, this representation is imperfect, since many interconnected "details" belonging to different layers are lost in the attempt of handling the complexity. This results in poor implementations and the design of mobile terminals is no exception. Wireless communication standards are often designed based on mathematical algorithms with theoretical boundaries, with few considerations to actual implementation constraints such as, energy consumption, silicon area, etc. This thesis does not try to remove the layer abstraction model, given its undeniable advantages, but rather uses those cross-layer "details" that went missing during the abstraction. This is done in three manners: In the first part, the cross-layer optimization is carried out from the algorithm perspective. Important circuit design parameters, such as quantization are taken into consideration when designing the algorithm for OFDM symbol timing, CFO, and SNR estimation with a single bit, namely, the Sign-Bit. Proof-of-concept circuits were fabricated and showed high potential for low-end receivers. In the second part, the cross-layer optimization is accomplished from the opposite side, i.e., the hardware-architectural side. A SDR architecture is known for its flexibility and scalability over many applications. In this work a filtering application is mapped into software instructions in the SDR architecture in order to make filtering-specific modules redundant, and thus, save silicon area. In the third and last part, the optimization is done from an intermediate point within the algorithm-architecture spectrum. Here, a heterogeneous architecture with a combination of highly efficient and highly flexible modules is used to accomplish initial synchronization in at least two concurrent OFDM standards. A demonstrator was build capable of performing synchronization in any two standards, including LTE, WiFi, and DVB-H

Sincronização de quadro e frequência para OFDM no padrão IEEE 802.15.4g : algoritmos e implementação em hardware

Orientadores: Renato da Rocha Lopes, Eduardo Rodrigues de LimaDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de ComputaçãoResumo: O objetivo deste trabalho é propor métodos de sincronização de quadro e de frequência de portadora para a camada física MR-OFDM do padrão IEEE 802.15.4g, começando pela pesquisa de algoritmos, passando pelas etapas de modelagem e simulação em alto nível, e finalmente implementando e avaliando os métodos propostos em hardware. A sincronização de quadro é o processo responsável por detectar o início do dado transmitido, ou seja, a primeira amostra válida do sinal de interesse. No caso de sistemas OFDM, onde o sinal transmitido é composto por um ou mais símbolos OFDM (cada símbolo sendo composto por uma quantidade fixa de amostras), o objetivo é detectar a borda ou janelamento de tais símbolos OFDM, ou seja, onde começa e termina cada um deles. A sincronização de frequência, por sua vez, consiste em estimar e compensar o erro de frequência de portadora, causado principalmente pelo descasamento dos osciladores do transmissor e do receptor. Com base em estudos preliminares, selecionamos o algoritmo de Minn para a detecção de quadro. Para a correção de erro de frequência, dividimos o processo em duas etapas, como é geralmente proposto na literatura: primeiro, o erro de frequência fracionário é estimado no domínio do tempo durante a detecção de quadro e compensado via rotação de sinal; após a conversão do domínio do tempo para o domínio da frequência, o erro de frequência inteiro é estimado e compensado utilizando um novo e simples algoritmo que será proposto e detalhado neste trabalho. Os algoritmos propostos foram implementados em hardware e uma plataforma de verificação baseada em FPGA foi criada para avaliar o seu desempenho. Os módulos implementados são parte de um projeto que está sendo desenvolvido no Instituto de Pesquisa Eldorado (Campinas) que tem como objetivo implementar em ASIC um transceptor compatível com o padrão IEEE 802.15.4gAbstract: The objective of this work is proposing methods of frame and frequency synchronization for the MR-OFDM PHY of IEEE 802.15.4g standard, starting with the research of state-of-the-art algorithms, passing through modeling, high-level simulations, and finally implementing and evaluating the proposed methods in hardware. Frame synchronization is the process responsible for detecting the beginning of transmitted data and, in the case of OFDM systems, the border of each OFDM symbol, while frequency synchronization consists of estimating and compensating the Carrier Frequency Offset (CFO) caused mainly by a mismatch between the transmitter and receiver oscillators. Based on the initial studies, we selected Minn¿s algorithm for frame detection. For the CFO correction, we split the process into two steps, as commonly proposed in the literature: first, the Fractional CFO is estimated in the time domain during the frame detection and compensated via signal rotation; after the conversion from time to frequency domain, the Integer CFO is estimated and compensated with a novel and simple algorithm that will be detailed in this work. The proposed algorithms were implemented in hardware and inserted in an FPGA-based verification platform for performance measurement. The implemented modules are part of a project that is under development at Eldorado Research Institute (Campinas) and aims to implement in ASIC a transceiver compliant to the IEEE 802.15.4g standardMestradoTelecomunicações e TelemáticaMestra em Engenharia Elétric

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5 dB for a PER = 10 -2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested. © 2011 Elsevier B.V. All rights reserved.This work was supported by the Spanish Ministerio de Educacion y Ciencia under grant TEC2008-06787.Canet Subiela, MJ.; Valls Coquillat, J.; Almenar Terré, V.; Marín-Roig Ramón, J. (2012). FPGA implementation of an OFDM-based WLAN receiver. Microprocessors and Microsystems. 36(3):232-244. https://doi.org/10.1016/j.micpro.2011.11.004S23224436

CYCLOSTATIONARY DETECTION FOR OFDM IN COGNITIVE RADIO SYSTEMS

Research on cognitive radio systems has attracted much interest in the last 10 years. Cognitive radio is born as a paradigm and since then the idea has seen contribution from technical disciplines under different conceptual layers. Since then improvements on processing capabilities have supported the current achievements and even made possible to move some of them from the research arena to markets. Cognitive radio implies a revolution that is even asking for changes in current business models, changes at the infrastructure levels, changes in legislation and requiring state of the art technology. Spectrum sensing is maybe the most important part of the cognitive radio system since it is the block designed to detect signal presence on the air. This thesis investigates what cognitive radio systems require, focusing on the spectrum sensing device. Two voice applications running under different Orthogonal Frequency Division Multiplexing (OFDM) schemes are chosen. These are WiFi and Wireless Microphone. Then, a Cyclostationary Spectrum Sensing technique is studied and applied to define a device capable of detecting OFDM signals in a noisy environment. One of the most interesting methodologies, in terms of complexity and computational requirements, known as FAM is developed. Study of the performance and frequency synchronization results are shown, including the development of a blind synchronization technique for offset estimation. 

CYCLOSTATIONARY DETECTION FOR OFDM IN COGNITIVE RADIO SYSTEMS

Research on cognitive radio systems has attracted much interest in the last 10 years. Cognitive radio is born as a paradigm and since then the idea has seen contribution from technical disciplines under different conceptual layers. Since then improvements on processing capabilities have supported the current achievements and even made possible to move some of them from the research arena to markets. Cognitive radio implies a revolution that is even asking for changes in current business models, changes at the infrastructure levels, changes in legislation and requiring state of the art technology. Spectrum sensing is maybe the most important part of the cognitive radio system since it is the block designed to detect signal presence on the air. This thesis investigates what cognitive radio systems require, focusing on the spectrum sensing device. Two voice applications running under different Orthogonal Frequency Division Multiplexing (OFDM) schemes are chosen. These are WiFi and Wireless Microphone. Then, a Cyclostationary Spectrum Sensing technique is studied and applied to define a device capable of detecting OFDM signals in a noisy environment. One of the most interesting methodologies, in terms of complexity and computational requirements, known as FAM is developed. Study of the performance and frequency synchronization results are shown, including the development of a blind synchronization technique for offset estimation.