Microfluidic cartridge with integrated array of amorphous silicon photosensors for chemiluminescence detection of viral DNA

Portable and simple analytical devices based on microfluidics with chemiluminescence detection are particularly attractive for point-of-care applications, offering high detectability and specificity in a simple and miniaturized analytical format. Particularly relevant for infectious disease diagnosis is the ability to sensitively and specifically detect target nucleic acid sequences in biological fluids. To reach the goal of real-life applications for such devices, however, several technological challenges related to full device integration are still to be solved, one key aspect regarding on-chip integration of the chemiluminescence signal detection device. Nowadays, the most promising approach is on-chip integration of thin-film photosensors. We recently proposed a portable cartridge with microwells aligned with an array of hydrogenated amorphous silicon (a-Si:H) photosensors, reaching attomole level limits of detection for different chemiluminescence model reactions. Herein, we explore its applicability and performance for multiplex and quantitative detection of viral DNA. In particular, the cartridge was modified to accommodate microfluidic channels and, upon immobilization of three oligonucleotide probes in different positions along each channel, each specific for a genotype of Parvovirus B19, viral nucleic acid sequences were captured and detected. With this system, taking advantage of oligoprobes specificity, chemiluminescence detectability, and photosensor sensitivity, accurate quantification of target analytes down to 70 pmol L-1 was obtained for each B19 DNA genotype, with high specificity and multiplexing ability. Results confirm the good detection capabilities and assay applicability of the proposed system, prompting the development of innovative portable analytical devices with enhanced sensitivity and multiplexed capabilities

Memory and information processing in neuromorphic systems

A striking difference between brain-inspired neuromorphic processors and current von Neumann processors architectures is the way in which memory and processing is organized. As Information and Communication Technologies continue to address the need for increased computational power through the increase of cores within a digital processor, neuromorphic engineers and scientists can complement this need by building processor architectures where memory is distributed with the processing. In this paper we present a survey of brain-inspired processor architectures that support models of cortical networks and deep neural networks. These architectures range from serial clocked implementations of multi-neuron systems to massively parallel asynchronous ones and from purely digital systems to mixed analog/digital systems which implement more biological-like models of neurons and synapses together with a suite of adaptation and learning mechanisms analogous to the ones found in biological nervous systems. We describe the advantages of the different approaches being pursued and present the challenges that need to be addressed for building artificial neural processing systems that can display the richness of behaviors seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed neuromorphic computing platforms and system

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Compact silicon photonics circuit to extract multiple parameters for process control monitoring

We present a compact interferometer circuit to extract multiple model parameters of on-chip waveguides and directional couplers from optical measurements. The compact design greatly improves the accuracy of extraction with fewer measurements, making it useful for process monitoring and detailed wafer-level variability analysis. We discuss the design requirements and illustrate the extraction using the Restart-CMA-ES global optimization algorithm. (C) 2020 Optical Society of America under the terms of the OSA Open Access Publishing Agreemen

A Comprehensive Workflow for General-Purpose Neural Modeling with Highly Configurable Neuromorphic Hardware Systems

In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromorphic hardware systems. We describe in detail a device with 45 million programmable and dynamic synapses that is currently under development, and we sketch the conceptual challenges that arise from taking this platform into operation. More specifically, we aim at the establishment of this neuromorphic system as a flexible and neuroscientifically valuable modeling tool that can be used by non-hardware-experts. We consider various functional aspects to be crucial for this purpose, and we introduce a consistent workflow with detailed descriptions of all involved modules that implement the suggested steps: The integration of the hardware interface into the simulator-independent model description language PyNN; a fully automated translation between the PyNN domain and appropriate hardware configurations; an executable specification of the future neuromorphic system that can be seamlessly integrated into this biology-to-hardware mapping process as a test bench for all software layers and possible hardware design modifications; an evaluation scheme that deploys models from a dedicated benchmark library, compares the results generated by virtual or prototype hardware devices with reference software simulations and analyzes the differences. The integration of these components into one hardware-software workflow provides an ecosystem for ongoing preparative studies that support the hardware design process and represents the basis for the maturity of the model-to-hardware mapping software. The functionality and flexibility of the latter is proven with a variety of experimental results

Edge Couplers with relaxed Alignment Tolerance for Pick-and-Place Hybrid Integration of III-V Lasers with SOI Waveguides

We report on two edge-coupling and power splitting devices for hybrid integration of III-V lasers with sub-micrometric silicon-on-insulator (SOI) waveguides. The proposed devices relax the horizontal alignment tolerances required to achieve high coupling efficiencies and are suitable for passively aligned assembly with pick-and-place tools. Light is coupled to two on-chip single mode SOI waveguides with almost identical power coupling efficiency, but with a varying relative phase accommodating the lateral misalignment between the laser diode and the coupling devices, and is suitable for the implementation of parallel optics transmitters. Experimental characterization with both a lensed fiber and a Fabry-P\'erot semiconductor laser diode has been performed. Excess insertion losses (in addition to the 3 dB splitting) taken as the worst case over both waveguides of respectively 2 dB and 3.1 dB, as well as excellent 1 dB horizontal loss misalignment ranges of respectively 2.8 um and 3.8 um (worst case over both in-plane axes) have been measured for the two devices. Back-reflections to the laser are below -20 dB for both devices within the 1 dB misalignment range. Devices were fabricated with 193 nm DUV optical lithography and are compatible with mass-manufacturing with mainstream CMOS technology