Multipair Full-Duplex Relaying with Massive Arrays and Linear Processing

We consider a multipair decode-and-forward relay channel, where multiple sources transmit simultaneously their signals to multiple destinations with the help of a full-duplex relay station. We assume that the relay station is equipped with massive arrays, while all sources and destinations have a single antenna. The relay station uses channel estimates obtained from received pilots and zero-forcing (ZF) or maximum-ratio combining/maximum-ratio transmission (MRC/MRT) to process the signals. To reduce significantly the loop interference effect, we propose two techniques: i) using a massive receive antenna array; or ii) using a massive transmit antenna array together with very low transmit power at the relay station. We derive an exact achievable rate in closed-form for MRC/MRT processing and an analytical approximation of the achievable rate for ZF processing. This approximation is very tight, especially for large number of relay station antennas. These closed-form expressions enable us to determine the regions where the full-duplex mode outperforms the half-duplex mode, as well as, to design an optimal power allocation scheme. This optimal power allocation scheme aims to maximize the energy efficiency for a given sum spectral efficiency and under peak power constraints at the relay station and sources. Numerical results verify the effectiveness of the optimal power allocation scheme. Furthermore, we show that, by doubling the number of transmit/receive antennas at the relay station, the transmit power of each source and of the relay station can be reduced by 1.5dB if the pilot power is equal to the signal power, and by 3dB if the pilot power is kept fixed, while maintaining a given quality-of-service

Rate-Splitting Robustness in Multi-Pair Massive MIMO Relay Systems

Relay systems improve both coverage and system capacity. Toward this direction, a full-duplex (FD) technology, being able to boost the spectral efficiency by transmitting and receiving simultaneously on the same frequency and time resources, is envisaged to play a key role in future networks. However, its benefits come at the expense of self-interference (SI) from their own transmit signal. At the same time, massive multiple-input massive multiple-output systems, bringing unconventionally many antennas, emerge as a promising technology with huge degrees-of-freedom. To this end, this paper considers a multi-pair decode-and-forward FD relay channel, where the relay station is deployed with a large number of antennas. Moreover, the rate-splitting (RS) transmission has recently been shown to provide significant performance benefits in various multi-user scenarios with imperfect channel state information at the transmitter (CSIT). Engaging the RS approach, we employ the deterministic equivalent analysis to derive the corresponding sum-rates in the presence of interferences. Initially, numerical results demonstrate the robustness of RS in half-duplex (HD) systems, since the achievable sum-rate increases without bound, i.e., it does not saturate at high signal-to-noise ratio. Next, we tackle the detrimental effect of SI in FD. In particular, and most importantly, not only FD outperforms HD, but also RS enables increasing the range of SI over which FD outperforms HD. Furthermore, increasing the number of relay station antennas, RS appears to be more efficacious due to imperfect CSIT, since SI decreases. Interestingly, increasing the number of users, the efficiency of RS worsens and its implementation becomes less favorable under these conditions. Finally, we verify that the proposed DEs, being accurate for a large number of relay station antennas, are tight approximations even for realistic system dimensions.Peer reviewedFinal Accepted Versio

Hardware-Conscious Wireless Communication System Design

The work at hand is a selection of topics in efficient wireless communication system design, with topics logically divided into two groups.One group can be described as hardware designs conscious of their possibilities and limitations. In other words, it is about hardware that chooses its configuration and properties depending on the performance that needs to be delivered and the influence of external factors, with the goal of keeping the energy consumption as low as possible. Design parameters that trade off power with complexity are identified for analog, mixed signal and digital circuits, and implications of these tradeoffs are analyzed in detail. An analog front end and an LDPC channel decoder that adapt their parameters to the environment (e.g. fluctuating power level due to fading) are proposed, and it is analyzed how much power/energy these environment-adaptive structures save compared to non-adaptive designs made for the worst-case scenario. Additionally, the impact of ADC bit resolution on the energy efficiency of a massive MIMO system is examined in detail, with the goal of finding bit resolutions that maximize the energy efficiency under various system setups.In another group of themes, one can recognize systems where the system architect was conscious of fundamental limitations stemming from hardware.Put in another way, in these designs there is no attempt of tweaking or tuning the hardware. On the contrary, system design is performed so as to work around an existing and unchangeable hardware limitation. As a workaround for the problematic centralized topology, a massive MIMO base station based on the daisy chain topology is proposed and a method for signal processing tailored to the daisy chain setup is designed. In another example, a large group of cooperating relays is split into several smaller groups, each cooperatively performing relaying independently of the others. As cooperation consumes resources (such as bandwidth), splitting the system into smaller, independent cooperative parts helps save resources and is again an example of a workaround for an inherent limitation.From the analyses performed in this thesis, promising observations about hardware consciousness can be made. Adapting the structure of a hardware block to the environment can bring massive savings in energy, and simple workarounds prove to perform almost as good as the inherently limited designs, but with the limitation being successfully bypassed. As a general observation, it can be concluded that hardware consciousness pays off