Composability and Predictability for Independent Application Development, Verification and Execution

System-on-chip (SOC) design gets increasingly complex, as a growing number of applications are integrated in modern systems. Some of these applications have real-time requirements, such as a minimum throughput or a maximum latency. To reduce cost, system resources are shared between applications, making their timing behavior inter-dependent. Real-time requirements must hence be verified for all possible combinations of concurrently executing applications, which is not feasible with commonly used simulation-based techniques. This chapter addresses this problem using two complexity-reducing concepts: composability and predictability. Applications in a composable system are completely isolated and cannot affect each other’s behaviors, enabling them to be independently verified. Predictable systems, on the other hand, provide lower bounds on performance, allowing applications to be verified using formal performance analysis. Five techniques to achieve composability and/or predictability in SOC resources are presented and we explain their implementation for processors, interconnect, and memories in our platform

Theoretical Design and Analysis of Multivolume Digital Assays with Wide Dynamic Range Validated Experimentally with Microfluidic Digital PCR

This paper presents a protocol using theoretical methods and free software to design and analyze multivolume digital PCR (MV digital PCR) devices; the theory and software are also applicable to design and analysis of dilution series in digital PCR. MV digital PCR minimizes the total number of wells required for “digital” (single molecule) measurements while maintaining high dynamic range and high resolution. In some examples, multivolume designs with fewer than 200 total wells are predicted to provide dynamic range with 5-fold resolution similar to that of single-volume designs requiring 12 000 wells. Mathematical techniques were utilized and expanded to maximize the information obtained from each experiment and to quantify performance of devices and were experimentally validated using the SlipChip platform. MV digital PCR was demonstrated to perform reliably, and results from wells of different volumes agreed with one another. No artifacts due to different surface-to-volume ratios were observed, and single molecule amplification in volumes ranging from 1 to 125 nL was self-consistent. The device presented here was designed to meet the testing requirements for measuring clinically relevant levels of HIV viral load at the point-of-care (in plasma, 1 000 000 molecules/mL), and the predicted resolution and dynamic range was experimentally validated using a control sequence of DNA. This approach simplifies digital PCR experiments, saves space, and thus enables multiplexing using separate areas for each sample on one chip, and facilitates the development of new high-performance diagnostic tools for resource-limited applications. The theory and software presented here are general and are applicable to designing and analyzing other digital analytical platforms including digital immunoassays and digital bacterial analysis. It is not limited to SlipChip and could also be useful for the design of systems on platforms including valve-based and droplet-based platforms. In a separate publication by Shen et al. (J. Am. Chem. Soc., 2011, DOI: 10.1021/ja2060116), this approach is used to design and test digital RT-PCR devices for quantifying RNA

Solución de predicción de temperaturas usando datos de un simulador térmico

The industry of integrated circuits is experiencing a moment of fierce change. As is, the methods used in all stages implied in its design process. The present work presents a method to predict temperatures for System on Chip (SoC) chiplet part with quite simple power map and a single thermal interface material using Machine Learning (ML) and its offspring Deep Learning (DL). The SoC part is represented as a response surface of a 2D model geometry surface used for a set of experiments to determine the relevant factors for the temperature prediction. In addition to the experiment design, a deployment strategy to implement a continuous integration and deployment process to be used for the target organization is also proposed. The idea is to achieve the principle of productive ML that states that models should be constantly learning by automating new data ingestion into the training process to enhance model performance in each of the cycle updates. The project proposes a method to strengthen the established thermal processes of the target organization by using ML tools and provide an alternative to speed up thermal model analysis using new available techniques derived from ML and Deep Learning

SoC-based FPGA architecture for image analysis and other highly demanding applications

Al giorno d'oggi, lo sviluppo di algoritmi si concentra su calcoli efficienti in termini di prestazioni ed efficienza energetica. Tecnologie come il field programmable gate array (FPGA) e il system on chip (SoC) basato su FPGA (FPGA/SoC) hanno dimostrato la loro capacità di accelerare applicazioni di calcolo intensive risparmiando al contempo il consumo energetico, grazie alla loro capacità di elevato parallelismo e riconfigurazione dell'architettura. Attualmente, i cicli di progettazione esistenti per FPGA/SoC sono lunghi, a causa della complessità dell'architettura. Pertanto, per colmare il divario tra le applicazioni e le architetture FPGA/SoC e ottenere un design hardware efficiente per l'analisi delle immagini e altri applicazioni altamente demandanti utilizzando lo strumento di sintesi di alto livello, vengono prese in considerazione due strategie complementari: tecniche ad hoc e stima delle prestazioni. Per quanto riguarda le tecniche ad-hoc, tre applicazioni molto impegnative sono state accelerate attraverso gli strumenti HLS: discriminatore di forme di impulso per i raggi cosmici, classificazione automatica degli insetti e re-ranking per il recupero delle informazioni, sottolineando i vantaggi quando questo tipo di applicazioni viene attraversato da tecniche di compressione durante il targeting dispositivi FPGA/SoC. Inoltre, in questa tesi viene proposto uno stimatore delle prestazioni per l'accelerazione hardware per prevedere efficacemente l'utilizzo delle risorse e la latenza per FPGA/SoC, costruendo un ponte tra l'applicazione e i domini architetturali. Lo strumento integra modelli analitici per la previsione delle prestazioni e un motore design space explorer (DSE) per fornire approfondimenti di alto livello agli sviluppatori di hardware, composto da due motori indipendenti: DSE basato sull'ottimizzazione a singolo obiettivo e DSE basato sull'ottimizzazione evolutiva multiobiettivo.Nowadays, the development of algorithms focuses on performance-efficient and energy-efficient computations. Technologies such as field programmable gate array (FPGA) and system on chip (SoC) based on FPGA (FPGA/SoC) have shown their ability to accelerate intensive computing applications while saving power consumption, owing to their capability of high parallelism and reconfiguration of the architecture. Currently, the existing design cycles for FPGA/SoC are time-consuming, owing to the complexity of the architecture. Therefore, to address the gap between applications and FPGA/SoC architectures and to obtain an efficient hardware design for image analysis and highly demanding applications using the high-level synthesis tool, two complementary strategies are considered: ad-hoc techniques and performance estimator. Regarding ad-hoc techniques, three highly demanding applications were accelerated through HLS tools: pulse shape discriminator for cosmic rays, automatic pest classification, and re-ranking for information retrieval, emphasizing the benefits when this type of applications are traversed by compression techniques when targeting FPGA/SoC devices. Furthermore, a comprehensive performance estimator for hardware acceleration is proposed in this thesis to effectively predict the resource utilization and latency for FPGA/SoC, building a bridge between the application and architectural domains. The tool integrates analytical models for performance prediction, and a design space explorer (DSE) engine for providing high-level insights to hardware developers, composed of two independent sub-engines: DSE based on single-objective optimization and DSE based on evolutionary multi-objective optimization

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems

On the evaluation of SEU effects on AXI interconnect within AP-SoCs

G-Programmable System-on-Chips offering the union of a processor system with a programmable hardware gave rise to applications that choose hardware acceleration to offload and parallelize computationally demanding tasks. Due to flexibility and performance they provide at low cost, these devices are also appealing for several applications in avionics, aerospace and automotive sectors, where reliability is the main concern. In particular, the interconnection architecture, and especially the AXI Interconnection for FPGA-accelerated applications, plays a critical role in these systems. This paper presents a reliability analysis of the AXI Interconnect IP Core implemented on Zynq-7000 AP-SoC against SEUs in the configuration memory of the programmable logic. The analysis has been conducted performing a fault injection campaign on the specific section of the configuration memory implementing the IP Core under test, which has been implemented within a benchmark design. The results are analyzed and classified, highlighting the criticality of the AXI Interconnect IP Core as a point of failure, especially for SEU-hardened hardware accelerator relying on mitigation techniques based on fine-grained and coarse-grained replication

Parallel-Pipelined-Memory (P2m) Of Blowfish Fpga-Based Radio System With Improved Power-Throughput For Secure Zigbee Transmission

Currently, the advanced encryption standard (AES) scheme is employed by most of the Institute of Electrical and Electronic Engineers (IEEE) standards to secure the data transmission of mobile devices specifically in internet of things (IoT) network. However, this scheme requires high compute platform and memory to support the encryption or decryption process which may not exist in all IoT-attached devices. In order to overcome this issue, this research work proposed an alternative cryptography scheme with improved power-throughput and reduced hardware utilization to be considered as a replacement to the existing AES. Based on the performance analysis among the symmetric cryptography schemes, the AES-128 and Blowfish schemes have been chosen to be enhanced and developed based on Zynq- 7000 field programmable gate array (FPGA) technology by using three design techniques comprised of parallel, pipelined and memory (P2M) techniques. At software level, the findings showed that the proposed Blowfish design had better performance with slices occupied and power consumption decreased by 45.3% and 94% respectively, and double throughput value was generated if compared to the proposed AES-128 design. Despite of these, the proposed AES-128 design increased the throughput by 22% and reduced the power consumed to 56% with 46.8% slices usage compared to the AES designs from previous studies. At hardware level, the proposed Blowfish design continued to be implemented and validated on ZedBoard and Zynq7000 AP SoC ZC702 FPGA platforms operated at 2.4 GHz ZigBee standard via XBee-PRO ZigBee through-hole XBP24CZ7PIT-004 for real-time data transmission. Two FPGA-based radio platforms were used as transmitter and receiver to form a two-way communication and measured in non-line-of-sight (NLOS) indoor environment based on point-to-point (P2P) topology within wireless personal area network (WPAN). The performance results indicated that the proposed P2M Blowfish radio system possessed a good quality in wireless data transmission with the bit-error-rate (BER) of 6.25x10-3, maximum signal strength of -34.58 dBm and maximum communication range of 61 m at 10 dBm transmitter radio frequency (RF) power level. The improvement in performance analysis either in the software or hardware level shown by the proposed P2M Blowfish has confirmed that this design has the ability to replace the existing AES scheme in mobile devices for the IoT application

Decompose and Conquer: Addressing Evasive Errors in Systems on Chip

Modern computer chips comprise many components, including microprocessor cores, memory modules, on-chip networks, and accelerators. Such system-on-chip (SoC) designs are deployed in a variety of computing devices: from internet-of-things, to smartphones, to personal computers, to data centers. In this dissertation, we discuss evasive errors in SoC designs and how these errors can be addressed efficiently. In particular, we focus on two types of errors: design bugs and permanent faults. Design bugs originate from the limited amount of time allowed for design verification and validation. Thus, they are often found in functional features that are rarely activated. Complete functional verification, which can eliminate design bugs, is extremely time-consuming, thus impractical in modern complex SoC designs. Permanent faults are caused by failures of fragile transistors in nano-scale semiconductor manufacturing processes. Indeed, weak transistors may wear out unexpectedly within the lifespan of the design. Hardware structures that reduce the occurrence of permanent faults incur significant silicon area or performance overheads, thus they are infeasible for most cost-sensitive SoC designs. To tackle and overcome these evasive errors efficiently, we propose to leverage the principle of decomposition to lower the complexity of the software analysis or the hardware structures involved. To this end, we present several decomposition techniques, specific to major SoC components. We first focus on microprocessor cores, by presenting a lightweight bug-masking analysis that decomposes a program into individual instructions to identify if a design bug would be masked by the program's execution. We then move to memory subsystems: there, we offer an efficient memory consistency testing framework to detect buggy memory-ordering behaviors, which decomposes the memory-ordering graph into small components based on incremental differences. We also propose a microarchitectural patching solution for memory subsystem bugs, which augments each core node with a small distributed programmable logic, instead of including a global patching module. In the context of on-chip networks, we propose two routing reconfiguration algorithms that bypass faulty network resources. The first computes short-term routes in a distributed fashion, localized to the fault region. The second decomposes application-aware routing computation into simple routing rules so to quickly find deadlock-free, application-optimized routes in a fault-ridden network. Finally, we consider general accelerator modules in SoC designs. When a system includes many accelerators, there are a variety of interactions among them that must be verified to catch buggy interactions. To this end, we decompose such inter-module communication into basic interaction elements, which can be reassembled into new, interesting tests. Overall, we show that the decomposition of complex software algorithms and hardware structures can significantly reduce overheads: up to three orders of magnitude in the bug-masking analysis and the application-aware routing, approximately 50 times in the routing reconfiguration latency, and 5 times on average in the memory-ordering graph checking. These overhead reductions come with losses in error coverage: 23% undetected bug-masking incidents, 39% non-patchable memory bugs, and occasionally we overlook rare patterns of multiple faults. In this dissertation, we discuss the ideas and their trade-offs, and present future research directions.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147637/1/doowon_1.pd

Direct and Non-Invasive Monitoring of Battery Internal State Via Novel GMI-IDT Magnetic Sensor

Efficient battery management systems (BMSs) in rechargeable battery-based systems require precise measurements of various battery parameters including state of charge (SOC), state of health (SOH) and charge capacity. Presently, SOC, charge capacity and SOH can only be indirectly inferred from long-term measurement of current, open circuit voltage (OCV), and temperature using multiple sensors. These techniques can only give an approximation of SOC and often require knowledge of the recent battery history to prevent excessive inaccuracy.To improve the performance of the BMS, an alternative method of monitoring the internal state of Li-ion batteries is presented here. Theoretical analysis of Li-ion batteries has indicated that the concentration of active lithium ions in the cathode is directly related to the magnetic susceptibility of the electrode materials. While charging/discharging, due to the change in the oxidation and/or spin state of metal atoms, the magnetic moment in the cathode varies. This indicates the potential for directly probing the internal state of the Li-ion batteries during charging/discharging by monitoring the changes in magnetic susceptibility via an appropriately designed magnetic sensor. In this research, a highly sensitive micromagnetic sensor design is investigated consisting of a single interdigital transducer (IDT) shunt-loaded with a magnetically sensitive Giant Magnetoimpedance (GMI) microwire. This design takes advantage of the coupling of the impedance characteristics of the GMI microwire to the IDT transduction process. The initial GMI-IDT sensor design is further developed and modified to maximize sensitivity and linearity. The sensor can detect magnetic field in the range of 900 nT and minute changes less than 1 μT when operated at or near its peak sensitivity. In addition, an appropriate procedure for preconditioning the GMI wire is developed to achieve sensor repeatability. Furthermore, using the identified optimum geometry of the experimental setup, the proposed sensor is implemented in monitoring the internal state of two types of Li-ion cells used in electric vehicles (EVs). The initial characterization results confirm that the GMI-IDT sensor can be used to directly monitor the charge capacity of the investigated Li-ion batteries. Other possible applications also include energy storage for renewable energy sources, and portable electronic devices