Improving the Spectral Efficiency of Nonlinear Satellite Systems through Time-Frequency Packing and Advanced Processing

We consider realistic satellite communications systems for broadband and broadcasting applications, based on frequency-division-multiplexed linear modulations, where spectral efficiency is one of the main figures of merit. For these systems, we investigate their ultimate performance limits by using a framework to compute the spectral efficiency when suboptimal receivers are adopted and evaluating the performance improvements that can be obtained through the adoption of the time-frequency packing technique. Our analysis reveals that introducing controlled interference can significantly increase the efficiency of these systems. Moreover, if a receiver which is able to account for the interference and the nonlinear impairments is adopted, rather than a classical predistorter at the transmitter coupled with a simpler receiver, the benefits in terms of spectral efficiency can be even larger. Finally, we consider practical coded schemes and show the potential advantages of the optimized signaling formats when combined with iterative detection/decoding.Comment: 8 pages, 8 figure

High performance faster-than-nyquist signaling

AbstractIn a wireless broadband context, multi-path dispersive channels can severely affectdata communication of Mobile Terminals (MTs) uplink.Single Carrier withFrequency-Domain Equalization (SC-FDE) has been proposed to deal with highlydispersive channels for the uplink of broadband wireless systems. However, currentsystems rely on older assumptions of the Nyquist theorem and assume that a systemneeds a minimum bandwidth 2Wper MT. Faster-Than-Nyquist (FTN) assumesthat it is possible to employ a bandwidth as low as 0.802 of the original Nyquistbandwidth with minimum loss - despite this, the current literature has only proposedcomplex receivers for a simple characterization of the wireless channel. Furthermore,the uplink of SC-FDE can be severely affected by a deep-fade and or poor channelconditions; to cope with such difficulties Diversity Combining (DC) Hybrid ARQ(H-ARQ) is a viable technique, since it combines the several packet copies sent bya MT to create reliable packet symbols at the receiver.In this thesis we consider the use of FTN signaling for the uplink of broadbandwireless systems employing SC-FDE based on the Iterative Block with DecisionFeedback Equalization (IB-DFE) receiver with a simple scheduled access HybridAutomatic Repeat reQuest (H-ARQ) specially designed taking into account thecharacteristics of FTN signals. This approach achieves a better performance thanNyquist signaling by taking advantage of the additional bandwidth employed of aroot-raised cosine pulse for additional diversity.Alongside a Packet Error Rate (PER) analytical model, simulation results show that this receiver presents a better performance when compared with a regular system,with higher system throughputs and a lower Energy per Useful Packet (EPUP)

Achievable Rate and Modulation for Bandlimited Channels with Oversampling and 1-Bit Quantization at the Receiver

Sustainably realizing applications of the future with high performance demands requires that energy efficiency becomes a central design criterion for the entire system. For example, the power consumption of the analog-to-digital converter (ADC) can become a major factor when transmitting at large bandwidths and carrier frequencies, e.g., for ultra-short range high data rate communication. The consumed energy per conversion step increases with the sampling rate such that high resolution ADCs become unfeasible in the sub-THz regime at the very high sampling rates required. This makes signaling schemes adapted to 1-bit quantizers a promising alternative. We therefore quantify the performance of bandlimited 1-bit quantized wireless communication channels using techniques like oversampling and faster-than-Nyquist (FTN) signaling to compensate for the loss of achievable rate. As a limiting case, we provide bounds on the mutual information rate of the hard bandlimited 1-bit quantized continuous-time – i.e., infinitely oversampled – additive white Gaussian noise channel in the mid-to-high signal-to-noise ratio (SNR) regime. We derive analytic expressions using runlength encoded input signals. For real signals the maximum value of the lower bound on the spectral efficiency in the high-SNR limit was found to be approximately 1.63 bit/s/Hz. Since in practical scenarios the oversampling ratio remains finite, we derive bounds on the achievable rate of the bandlimited oversampled discrete-time channel. These bounds match the results of the continuous-time channel remarkably well. We observe spectral efficiencies up to 1.53 bit/s/Hz in the high-SNR limit given hard bandlimitation. When excess bandwidth is tolerable, spectral efficiencies above 2 bit/s/Hz per domain are achievable w.r.t. the 95 %-power containment bandwidth. Applying the obtained bounds to a bandlimited oversampled 1-bit quantized multiple-input multiple-output channel, we show the benefits when using appropriate power allocation schemes. As a constant envelope modulation scheme, continuous phase modulation is considered in order to relieve linearity requirements on the power amplifier. Noise-free performance limits are investigated for phase shift keying (PSK) and continuous phase frequency shift keying (CPFSK) using higher-order modulation alphabets and intermediate frequencies. Adapted waveforms are designed that can be described as FTN-CPFSK. With the same spectral efficiency in the high-SNR limit as PSK and CPFSK, these waveforms provide a significantly improved bit error rate (BER) performance. The gain in SNR required for achieving a certain BER can be up to 20 dB.Die nachhaltige Realisierung von zukünftigen Übertragungssystemen mit hohen Leistungsanforderungen erfordert, dass die Energieeffizienz zu einem zentralen Designkriterium für das gesamte System wird. Zum Beispiel kann die Leistungsaufnahme des Analog-Digital-Wandlers (ADC) zu einem wichtigen Faktor bei der Übertragung mit großen Bandbreiten und Trägerfrequenzen werden, z. B. für die Kommunikation mit hohen Datenraten über sehr kurze Entfernungen. Die verbrauchte Energie des ADCs steigt mit der Abtastrate, so dass hochauflösende ADCs im Sub-THz-Bereich bei den erforderlichen sehr hohen Abtastraten schwer einsetzbar sind. Dies macht Signalisierungsschemata, die an 1-Bit-Quantisierer angepasst sind, zu einer vielversprechenden Alternative. Wir quantifizieren daher die Leistungsfähigkeit von bandbegrenzten 1-Bit-quantisierten drahtlosen Kommunikationssystemen, wobei Techniken wie Oversampling und Faster-than-Nyquist (FTN) Signalisierung eingesetzt werden, um den durch Quantisierung verursachten Verlust der erreichbaren Rate auszugleichen. Wir geben Grenzen für die Transinformationsrate des Extremfalls eines strikt bandbegrenzten 1-Bit quantisierten zeitkontinuierlichen – d.h. unendlich überabgetasteten – Kanals mit additivem weißen Gauß’schen Rauschen bei mittlerem bis hohem Signal-Rausch-Verhältnis (SNR) an. Wir leiten analytische Ausdrücke basierend auf lauflängencodierten Eingangssignalen ab. Für reelle Signale ist der maximale Wert der unteren Grenze der spektralen Effizienz im Hoch-SNR-Bereich etwa 1,63 Bit/s/Hz. Da die Überabtastrate in praktischen Szenarien endlich bleibt, geben wir Grenzen für die erreichbare Rate eines bandbegrenzten, überabgetasteten zeitdiskreten Kanals an. Diese Grenzen stimmen mit den Ergebnissen des zeitkontinuierlichen Kanals bemerkenswert gut überein. Im Hoch-SNR-Bereich sind spektrale Effizienzen bis zu 1,53 Bit/s/Hz bei strikter Bandbegrenzung möglich. Wenn Energieanteile außerhalb des Frequenzbandes tolerierbar sind, können spektrale Effizienzen über 2 Bit/s/Hz pro Domäne – bezogen auf die Bandbreite, die 95 % der Energie enthält – erreichbar sein. Durch die Anwendung der erhaltenen Grenzen auf einen bandbegrenzten überabgetasteten 1-Bit quantisierten Multiple-Input Multiple-Output-Kanal zeigen wir Vorteile durch die Verwendung geeigneter Leistungsverteilungsschemata. Als Modulationsverfahren mit konstanter Hüllkurve betrachten wir kontinuierliche Phasenmodulation, um die Anforderungen an die Linearität des Leistungsverstärkers zu verringern. Beschränkungen für die erreichbare Datenrate bei rauschfreier Übertragung auf Zwischenfrequenzen mit Modulationsalphabeten höherer Ordnung werden für Phase-shift keying (PSK) and Continuous-phase frequency-shift keying (CPFSK) untersucht. Weiterhin werden angepasste Signalformen entworfen, die als FTN-CPFSK beschrieben werden können. Mit der gleichen spektralen Effizienz im Hoch-SNR-Bereich wie PSK und CPFSK bieten diese Signalformen eine deutlich verbesserte Bitfehlerrate (BER). Die Verringerung des erforderlichen SNRs zur Erreichung einer bestimmten BER kann bis zu 20 dB betragen

A combined PSK/ASK transmission system for commercial telephony via satellite

This study addresses three modulation schemes capable of increasing the voice channel capacity of the INTELSAT TDMA/DSI System operating with INTELSAT V spacecraft. In particular, a combination digital Amplitude-Shift Keying/Phase-Shifting Keying (APK) technique is evaluated with respect to signal design, thermal noise performance, bandwidths limitations, co-channel interference, adjacent channel interference, TWT distortion and modem complexity in an INTELSAT TDMA system environment. In a linear channel some APK signal designs are known to require significantly less average SNR than PSK to achieve the same probability of symbol error. However, when operated through a satellite channel containing at least one TWT, the reduction in average power required to accommodate amplitude variations causes APK performance to fall below that of PSK for the same alphabet size. Signal predistortion and/or TWT linearization can eliminate the effect of TWT distortion and restore the performance advantage, although the overall performance of APK is still inferior to PSK. However, in a heavily interference limited environment, such as INTELSAT V, the lower average power requirements caused an APK system to perform better, in some cases considerably better, than the corresponding PSK case. Modem implementation considerations include how the signal set can be generated, the type and method of predistortion compensation, the detection method and the equipment required for the reconstruction of phase and amplitude references. The evaluation techniques of APK described include mathematical models, computer simulations (including the development of a unified error performance expression) and logical extrapolation from the QPSK case. Finally, a simple 8 level APK hardware modem was constructed and evaluated. It is concluded that an APK system may be of advantage as a retrofit in the INTELSAT TDMA system operating at 6/4 GHz, but be of significant advantage at 14/11 Ghz where the higher signal/noise ratios can yield an increase in capacity of up to 50 percent

Analysis and Design of High Speed Serial Interfaces for Automotive Applications

The demand for an enriched end-user experience and increased performance in next generation electronic applications is never ending, and it is a common trend for a wide spectrum of applications owing to different markets, like computing, mobile communication and automotive. For this reason High Speed Serial Interface have become widespread components for nowadays electronics with a constant demand for power reduction and data rate increase. In the frame of gigabit serial systems, the work discussed in this thesis develops in two directions: on one hand, the aim is to support the continuous data rate increase with the development of novel link modeling approaches that will be employed for system level evaluation and as support in the design and characterization phases. On the other hand, the design considerations and challenges in the implementation of the transmitter, one of the most delicate blocks for the signal integrity performance of the link, are central. The first part of the activity regarding link performance predictions lead to the development of an enhanced statistical simulation approach, capable to account for the transmitter waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe- art simulation approaches. The proposed approach has been extensively tested by comparison with traditional simulation approaches (Spice-like simulators) and validated against experimental characterization of a test system, with satisfactory results. The second part of the activity consists in the design of a high speed transmitter in a deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter implementation, and reduce the power dissipation adopting a voltage mode architecture. The experimental characterization of the fabricated lot draws a twofold picture, with some of the performance figures showing a very good qualitative and quantitative agreement with pre-silicon simulations, and others revealing a poor performance level, especially for the eye diagram. Investigation of the root causes by the analysis of the physical silicon design, of the bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse. Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione. Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore. La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta \ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con risultati pienamente soddisfacenti. La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione, mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le linee guida da seguire nella futura progettazione di un nuovo prototipo