Combining Time-Triggered Plans with Priority Scheduled Task Sets

The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-319-39083-3_13Time-triggered and concurrent priority-based scheduling are the two major approaches in use for real-time and embedded systems. Both approaches have their own advantages and drawbacks. On the one hand, priority-based systems facilitate separation of concerns between functional and timing requirements by relying on an underlying real- time operating system that takes all scheduling decisions at run time. But this is at the cost of indeterminism in the exact timing pattern of execution of activities, namely variable release jitter. On the other hand, time-triggered schedules are more intricate to design since all schedul- ing decisions must be taken beforehand in the design phase, but their advantage is determinism and more chances for minimisation of release jitter. In this paper we propose a software architecture that enables the combined and controlled execution of time-triggered plans and priority- scheduled tasks. We also describe the implementation of an Ada library supporting it. Our aim is to take advantage of the best of both ap- proaches by providing jitter-controlled execution of time-triggered tasks (e.g., control tasks), coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements.This work has been partly supported by the Spanish Government’s project M2C2 (TIN2014-56158-C4-1-P-AR) and the European Commission’s project EMC2 (ARTEMIS-JU Call 2013 AIPP-5, Contract 621429).Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2016). Combining Time-Triggered Plans with Priority Scheduled Task Sets. En Reliable Software Technologies – Ada-Europe 2016. Springer. 195-212. https://doi.org/10.1007/978-3-319-39083-3_13S195212Liu, C., Layland, J.: Scheduling algorithms for multiprogramming in a hard real-time environment. J. ACM 20(1), 46–61 (1973)Martí, P., Fuertes, J., Fohler, G.: Jitter compensation for real-time control systems. In: Real-Time Systems Symposium (2001)Dobrin, R.: Combining off-line schedule construction and fixed priority scheduling in real-time computer systems. Ph.D. thesis. Mälardalen University (2005)Cervin, A.: Integrated control and real-time scheduling. Ph.D. thesis. Lund Institute of Technology, April 2003Balbastre, P., Ripoll, I., Vidal, J., Crespo, A.: A task model to reduce control delays. Real-Time Syst. 27(3), 215–236 (2004)Hong, S., Hu, X., Lemmon, M.: Reducing delay jitter of real-time control tasks through adaptive deadline adjustments. In: 22nd Euromicro Conference on Real-Time Systems - ECRTS, pp. 229–238. IEEE Computer Society (2010)ISO/IEC-JTC1-SC22-WG9: Ada Reference Manual ISO/IEC 8652:2012(E) (2012). http://www.ada-europe.org/manuals/LRM-2012.pdfBaker, T.P., Shaw, A.: The cyclic executive model and Ada. In: Proceedings IEEE Real Time Systems Symposium 1988, Huntsville, Alabama, pp. 120–129 (1988)Liu, J.W.S.: Real-Time Systems. Prentice-Hall Inc., Upper Saddle River (2000)Pont, M.J.: The Engineering of Reliable Embedded Systems: LPC1769. SafeTTy Systems Limited, Skelmersdale (2014). ISBN: 978-0-9930355-0-0Aldea Rivas, M., González Harbour, M.: MaRTE OS: an Ada kernel for real-time embedded applications. In: Strohmeier, A., Craeynest, D. (eds.) Ada-Europe 2001. LNCS, vol. 2043, pp. 305–316. Springer, Heidelberg (2001)Palencia, J., González-Harbour, M.: Schedulability analysis for tasks with static and dynamic offsets. In: 9th IEEE Real-Time Systems Symposium (1998)Wellings, A.J., Burns, A.: A framework for real-time utilities for Ada 2005. Ada Lett. XXVI XXVII(2), 41–47 (2007)Real, J., Crespo, A.: Incorporating operating modes to an Ada real-time framework. Ada Lett. 30(1), 73–85 (2010)Sáez, S., Terrasa, S., Crespo, A.: A real-time framework for multiprocessor platforms using Ada 2012. In: Romanovsky, A., Vardanega, T. (eds.) Ada-Europe 2011. LNCS, vol. 6652, pp. 46–60. Springer, Heidelberg (2011

Software dependability modeling using an industry-standard architecture description language

Performing dependability evaluation along with other analyses at architectural level allows both making architectural tradeoffs and predicting the effects of architectural decisions on the dependability of an application. This paper gives guidelines for building architectural dependability models for software systems using the AADL (Architecture Analysis and Design Language). It presents reusable modeling patterns for fault-tolerant applications and shows how the presented patterns can be used in the context of a subsystem of a real-life application

Real-time on-board obstacle avoidance for UAVs based on embedded stereo vision

In order to improve usability and safety, modern unmanned aerial vehicles (UAVs) are equipped with sensors to monitor the environment, such as laser-scanners and cameras. One important aspect in this monitoring process is to detect obstacles in the flight path in order to avoid collisions. Since a large number of consumer UAVs suffer from tight weight and power constraints, our work focuses on obstacle avoidance based on a lightweight stereo camera setup. We use disparity maps, which are computed from the camera images, to locate obstacles and to automatically steer the UAV around them. For disparity map computation we optimize the well-known semi-global matching (SGM) approach for the deployment on an embedded FPGA. The disparity maps are then converted into simpler representations, the so called U-/V-Maps, which are used for obstacle detection. Obstacle avoidance is based on a reactive approach which finds the shortest path around the obstacles as soon as they have a critical distance to the UAV. One of the fundamental goals of our work was the reduction of development costs by closing the gap between application development and hardware optimization. Hence, we aimed at using high-level synthesis (HLS) for porting our algorithms, which are written in C/C++, to the embedded FPGA. We evaluated our implementation of the disparity estimation on the KITTI Stereo 2015 benchmark. The integrity of the overall realtime reactive obstacle avoidance algorithm has been evaluated by using Hardware-in-the-Loop testing in conjunction with two flight simulators.Comment: Accepted in the International Archives of the Photogrammetry, Remote Sensing and Spatial Information Scienc