Testing microelectronic biofluidic systems

According to the 2005 International Technology Roadmap for Semiconductors, the integration of emerging nondigital CMOS technologies will require radically different test methods, posing a major challenge for designers and test engineers. One such technology is microelectronic fluidic (MEF) arrays, which have rapidly gained importance in many biological, pharmaceutical, and industrial applications. The advantages of these systems, such as operation speed, use of very small amounts of liquid, on-board droplet detection, signal conditioning, and vast digital signal processing, make them very promising. However, testable design of these devices in a mass-production environment is still in its infancy, hampering their low-cost introduction to the market. This article describes analog and digital MEF design and testing method

SLAM : an automated structure to layout synthesis system

SLAM is a structure to layout synthesis system. It incorporates parameterisable bit-sliced and glue-logic generators to produce high density layout. In this paper, we describe a sliced layout architecture and SLAM system. In addition, we present partitioning algorithms for generating the floorplan for such an architecture. The algorithms partition the netlist into component sets best suited for different layout styles such as bit-sliced or strip-oriented logic. Each group is partitioned further into clusters to achieve better area utilization. Several experiments demonstrate that highly dense layouts can be achieved by using these algorithms with the sliced layout architecture

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations