Lex-Partitioning: A New Option for BDD Search

For the exploration of large state spaces, symbolic search using binary decision diagrams (BDDs) can save huge amounts of memory and computation time. State sets are represented and modified by accessing and manipulating their characteristic functions. BDD partitioning is used to compute the image as the disjunction of smaller subimages. In this paper, we propose a novel BDD partitioning option. The partitioning is lexicographical in the binary representation of the states contained in the set that is represented by a BDD and uniform with respect to the number of states represented. The motivation of controlling the state set sizes in the partitioning is to eventually bridge the gap between explicit and symbolic search. Let n be the size of the binary state vector. We propose an O(n) ranking and unranking scheme that supports negated edges and operates on top of precomputed satcount values. For the uniform split of a BDD, we then use unranking to provide paths along which we partition the BDDs. In a shared BDD representation the efforts are O(n). The algorithms are fully integrated in the CUDD library and evaluated in strongly solving general game playing benchmarks.Comment: In Proceedings GRAPHITE 2012, arXiv:1210.611

Discrete Function Representations Utilizing Decision Diagrams and Spectral Techniques

All discrete function representations become exponential in size in the worst case. Binary decision diagrams have become a common method of representing discrete functions in computer-aided design applications. For many functions, binary decision diagrams do provide compact representations. This work presents a way to represent large decision diagrams as multiple smaller partial binary decision diagrams. In the Boolean domain, each truth table entry consisting of a Boolean value only provides local information about a function at that point in the Boolean space. Partial binary decision diagrams thus result in the loss of information for a portion of the Boolean space. If the function were represented in the spectral domain however, each integer-valued coefficient would contain some global information about the function. This work also explores spectral representations of discrete functions, including the implementation of a method for transforming circuits from netlist representations directly into spectral decision diagrams

Probabilistic representation and manipulation of Boolean functions using free Boolean diagrams

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 145-149).by Amelia Huimin Shen.Ph.D

Computing leakage current distributions and determination of minimum leakage vectors for combinational designs

Analyzing circuit leakage and minimizing leakage during the standby mode of oper- ation of a circuit are important problems faced during contemporary circuit design. Analysis of the leakage profiles of an implementation would enable a designer to select between several implementations in a leakage optimal way. Once such an im- plementation is selected, minimizing leakage during standby operation (by finding the minimum leakage state over all input vector states) allows further power reduc- tions. However, both these problems are NP-hard. Since leakage power is currently approaching about half the total circuit power, these two problems are of prime rel- evance. This thesis addresses these NP-hard problems. An Algebraic Decision Diagram (ADD) based approach to determine and implicitly represent the leakage value for all input vectors of a combinational circuit is presented. In its exact form, this technique can compute the leakage value of each input vector, by storing these leakage values implicitly in an ADD structure. To broaden the applicability of this technique, an approximate version of the algorithm is presented as well. The approximation is done by limiting the total number of discriminant nodes in any ADD. It is experimentally demonstrated that these approximate techniques produce results with quantifiable errors. In particular, it is shown that limiting the number of discriminants to a value between 12 and 16 is practical, allowing for good accuracy and lowered memory utilization. In addition, a heuristic approach to determine the input vector which minimizes leakage for a combinational design is presented. Approximate signal probabilities of internal nodes are used as a guide in finding the minimum leakage vector. Probabilistic heuristics are used to select the next gate to be processed, as well as to select the best state of the selected gate. A fast satisfiability solver is employed to ensure the consistency of the assignments that are made in this process. Experimental results indicate that this method has very low run-times, with excellent accuracy, compared to existing approaches

Automated synthesis and optimization of multilevel logic circuits.

With the increased complexity of Very Large Scaled Integrated (VLSI) circuits, multilevellogic synthesis plays an even more important role due to its flexibility and compactness.The history of symbolic logic and some typical techniques for multilevel logic synthesisare reviewed. These methods include algorithmic approach; Rule-Based approach; BinaryDecision Diagram (BDD) approach; Field Programmable Gate Array(FPGA) approachand several perturbation applications.One new kind of don't cares (DCs), called functional DCs has been proposed for multilevellogic synthesis. The conventional two-level cubes are generalized to multilevel cubes.Then functional DCs are generated based on the properties of containment. The conceptof containment is more general than unateness which leads to the generation of newDCs. A separate C program has been developed to utilize the functional DCs generatedas a Boolean function is decomposed for both single output and multiple output functions.The program can produce better results than script.rugged of SIS, developed by UC Berkeley,both in area and speed in less CPU time for a number of testcases from MCNC andIWLS'93 benchmarks.In certain applications ANDjXOR (Reed-Muller) logic has shown some attractive advantagesover the standard Boolean logic based on AND JOR operations. A bidirectionalconversion algorithm between these two paradigms is presented based on the concept of polarityfor sum-of-products (SOP) Boolean functions, multiple segment and multiple pointerfacilities. Experimental results show that the algorithm is much faster than the previouslypublished programs for any fixed polarity. Based on this algorithm, a new technique calledredundancy-removal is applied to generalize the idea to very large multiple output Booleanfunctions. Results for benchmarks with up to 199 inputs and 99 outputs are presented.Applying the preceding conversion program, any Boolean functions can be expressedby fixed polarity Reed-Muller forms. There are 2n polarities for an n-variable function andthe number of product terms depends on these polarities. The problem of exact polarityminimization is computationally extensive and current programs are only suitable whenn :::; 15. Based on the comparison of the concepts of polarity in the standard Boolean logicand Reed-Muller logic, a fast algorithm is developed and implemented in C language whichcan find the best polarity for multiple output functions. Benchmark examples of up to 25inputs and 29 outputs run on a personal computer are given.After the best polarity for a Boolean function is calculated, this function can be furthersimplified using mixed polarity methods by combining the adjacent product terms. Hence,an efficient program is developed based on decomposition strategy to implement mixedpolarity minimization for both single output and very large multiple output Boolean functions.Experimental results show that the numbers of product terms are much less thanthe results produced by ESPRESSO for some categories of functions