PERFORMANCE COMPARISON OF NON-INTERLEAVED BCH CODES AND INTERLEAVED BCH CODES

This project covers the research about the BCH error correcting codes and the performance of interleaved and non-interleaved BCH codes. Both long and short BCH codes for multimedia communication are examined in an A WGN channel. Algorithm for simulating the BCH codes was also being investigated, which includes generating the parity check matrix, generating the message code in Galois array matrix, encoding the message blocks, modulation and decoding the message blocks. Algorithm for interleaving that includes interleaving message, including burst errors and deinterleaving message is combined with the BCH codes algorithm for simulating the interleaved BCH codes. The performance and feasibility of the coding structure are tested. The performance comparison between interleaved and noninterleaved BCH codes is studied in terms of error performance, channel performance and effect of data rates on the bit error rate (BER). The Berlekamp-Massey Algorithm decoding scheme was implemented. Random integers are generated and encoded with BCH encoder. Burst errors are added before the message is interleaved, then enter modulation and channel simulation. Interleaved message is then compared with noninterleaved message and the error statistics are compared. Initially, certain amount of burst errors is used. "ft is found that the graph does not agree with the theoretical bit error rate (BER) versus signal-to-noise ratio (SNR). When compared between each BCH codeword (i.e. n = 31, n = 63 and n = 127), n = 31 shows the highest BER while n = 127 shows the lowest BER. This happened because of the occurrence of error bursts and also due to error frequency. A reduced size or errors from previous is used in the algorithm. A graph similar to the theoretical BER vs SNR is obtained for both interleaved and non-interleaved BCH codes. It is found that BER of non-interleaved is higher than interleaved BCH codes as SNR increases. These observations show that size of errors influence the effect of interleaving. Simulation time is also studied in terms of block length. It is found that interleaved BCH codes consume longer simulation time compared to non-interleaved BCH codes due to additional algorithm for the interleaved BCH codes

A VLSI synthesis of a Reed-Solomon processor for digital communication systems

The Reed-Solomon codes have been widely used in digital communication systems such as computer networks, satellites, VCRs, mobile communications and high- definition television (HDTV), in order to protect digital data against erasures, random and burst errors during transmission. Since the encoding and decoding algorithms for such codes are computationally intensive, special purpose hardware implementations are often required to meet the real time requirements. -- One motivation for this thesis is to investigate and introduce reconfigurable Galois field arithmetic structures which exploit the symmetric properties of available architectures. Another is to design and implement an RS encoder/decoder ASIC which can support a wide family of RS codes. -- An m-programmable Galois field multiplier which uses the standard basis representation of the elements is first introduced. It is then demonstrated that the exponentiator can be used to implement a fast inverter which outperforms the available inverters in GF(2m). Using these basic structures, an ASIC design and synthesis of a reconfigurable Reed-Solomon encoder/decoder processor which implements a large family of RS codes is proposed. The design is parameterized in terms of the block length n, Galois field symbol size m, and error correction capability t for the various RS codes. The design has been captured using the VHDL hardware description language and mapped onto CMOS standard cells available in the 0.8-µm BiCMOS design kits for Cadence and Synopsys tools. The experimental chip contains 218,206 logic gates and supports values of the Galois field symbol size m = 3,4,5,6,7,8 and error correction capability t = 1,2,3, ..., 16. Thus, the block length n is variable from 7 to 255. Error correction t and Galois field symbol size m are pin-selectable. -- Since low design complexity and high throughput are desired in the VLSI chip, the algebraic decoding technique has been investigated instead of the time or transform domain. The encoder uses a self-reciprocal generator polynomial which structures the codewords in a systematic form. At the beginning of the decoding process, received words are initially stored in the first-in-first-out (FIFO) buffer as they enter the syndrome module. The Berlekemp-Massey algorithm is used to determine both the error locator and error evaluator polynomials. The Chien Search and Forney's algorithms operate sequentially to solve for the error locations and error values respectively. The error values are exclusive or-ed with the buffered messages in order to correct the errors, as the processed data leave the chip

Hardware Obfuscation for Finite Field Algorithms

With the rise of computing devices, the security robustness of the devices has become of utmost importance. Companies invest huge sums of money, time and effort in security analysis and vulnerability testing of their software products. Bug bounty programs are held which incentivize security researchers for finding security holes in software. Once holes are found, software firms release security patches for their products. The semiconductor industry has flourished with accelerated innovation. Fabless manufacturing has reduced the time-to-market and lowered the cost of production of devices. Fabless paradigm has introduced trust issues among the hardware designers and manufacturers. Increasing dependence on computing devices in personal applications as well as in critical infrastructure has given a rise to hardware attacks on the devices in the last decade. Reverse engineering and IP theft are major challenges that have emerged for the electronics industry. Integrated circuit design companies experience a loss of billions of dollars because of malicious acts by untrustworthy parties involved in the design and fabrication process, and because of attacks by adversaries on the electronic devices in which the chips are embedded. To counter these attacks, researchers have been working extensively towards finding strong countermeasures. Hardware obfuscation techniques make the reverse engineering of device design and functionality difficult for the adversary. The goal is to conceal or lock the underlying intellectual property of the integrated circuit. Obfuscation in hardware circuits can be implemented to hide the gate-level design, layout and the IP cores. Our work presents a novel hardware obfuscation design through reconfigurable finite field arithmetic units, which can be employed in various error correction and cryptographic algorithms. The effectiveness and efficiency of the proposed methods are verified by an obfuscated Reformulated Inversion-less Berlekamp-Massey (RiBM) architecture based Reed-Solomon decoder. Our experimental results show the hardware implementation of RiBM based Reed-Solomon decoder built using reconfigurable field multiplier designs. The proposed design provides only very low overhead with improved security by obfuscating the functionality and the outputs. The design proposed in our work can also be implemented in hardware designs of other algorithms that are based on finite field arithmetic. However, our main motivation was to target encryption and decryption circuits which store and process sensitive data and are used in critical applications

Authentication Schemes based on Physically Unclonable Functions

In this project we investigate dierent hardware authentication schemes based on Physically Unclonable Functions. We start by analyzing the concepts of a fuzzy extractor and a secure sketch from an information-theoretic perspective. We then present a hardware implementation of a fuzzy extractor which uses the code oset construction with BCH codes. Finally, we propose a new cryptographic protocol for PUF authentication based upon polynomial interpolation using Sudan\u27s list-decoding algorithm. We provide preliminary results into the feasibility of this protocol, by looking at the practicality of nding a polynomial that can be assigned as a cryptographic key to each device

Authentication Schemes based on Physically Unclonable Functions

In this project we investigate different hardware authentication schemes based on Physically Unclonable Functions. We start by analyzing the concepts of a fuzzy extractor and a secure sketch from an information-theoretic perspective. We then present a hardware implementation of a fuzzy extractor which uses the code offset construction with BCH codes. Finally, we propose a new cryptographic protocol for PUF authentication based upon polynomial interpolation using Sudan\u27s list-decoding algorithm. We provide preliminary results into the feasibility of this protocol, by looking at the practicality of finding a polynomial that can be assigned as a cryptographic key to each device

PERFORMANCE COMPARISON OF NON-INTERLEAVED BCH CODES AND INTERLEAVED BCH CODES

This project covers the research about the BCH error correcting codes and the performance of interleaved and non-interleaved BCH codes. Both long and short BCH codes for multimedia communication are examined in an A WGN channel. Algorithm for simulating the BCH codes was also being investigated, which includes generating the parity check matrix, generating the message code in Galois array matrix, encoding the message blocks, modulation and decoding the message blocks. Algorithm for interleaving that includes interleaving message, including burst errors and deinterleaving message is combined with the BCH codes algorithm for simulating the interleaved BCH codes. The performance and feasibility of the coding structure are tested. The performance comparison between interleaved and noninterleaved BCH codes is studied in terms of error performance, channel performance and effect of data rates on the bit error rate (BER). The Berlekamp-Massey Algorithm decoding scheme was implemented. Random integers are generated and encoded with BCH encoder. Burst errors are added before the message is interleaved, then enter modulation and channel simulation. Interleaved message is then compared with noninterleaved message and the error statistics are compared. Initially, certain amount of burst errors is used. "ft is found that the graph does not agree with the theoretical bit error rate (BER) versus signal-to-noise ratio (SNR). When compared between each BCH codeword (i.e. n = 31, n = 63 and n = 127), n = 31 shows the highest BER while n = 127 shows the lowest BER. This happened because of the occurrence of error bursts and also due to error frequency. A reduced size or errors from previous is used in the algorithm. A graph similar to the theoretical BER vs SNR is obtained for both interleaved and non-interleaved BCH codes. It is found that BER of non-interleaved is higher than interleaved BCH codes as SNR increases. These observations show that size of errors influence the effect of interleaving. Simulation time is also studied in terms of block length. It is found that interleaved BCH codes consume longer simulation time compared to non-interleaved BCH codes due to additional algorithm for the interleaved BCH codes

A Comparison Study of LDPC and BCH Codes

The need for efficient and reliable digital data communication systems has been rising rapidly in recent years. There are various reasons that have brought this need for the communication systems, among them are the increase in automatic data processing equipment and the increased need for long range communication. Therefore, the LDPC and BCH codes were developed for achieving more reliable data transmission in communication systems. This project covers the research about the LDPC and BCH error correction codes. Algorithm for simulating both the LDPC and BCH codes were also being investigated, which includes generating the parity check matrix, generating the message code in Galois array matrix, encoding the message bits, modulation and decoding the message bits for LDPC. Matlab software is used for encoding and decoding the codes. The percentage of accuracy for LDPC simulation codes are ranging from 95% to 99%. The results obtained shows that the LDPC codes are more efficient and reliable than the BCH codes coding method of error correction because the LDPC codes had a channel performance very close to the Shannon limit. LDPC codes are a class of linear block codes that are proving to be the best performing forward error correction available. Markets such as broadband wireless and mobile networks operate in noisy environments and need powerful error correction in order to improve reliability and better data rates. Through LDPC and BCH codes, these systems can operate more reliably, efficiently and at higher data rates

Simulation of Error Correction Algorithms Using Reed Solomon Codes

The Reed-Solomon codes for multiple-error-correction are examined in this study. The results of a comparison between the conventional Gorenstein-Zierler method and a transform method are discussed, and simple examples are given. Then decoding algorithms are compared in terms of the numerical complexity. Finally the conclusions of the simulation are stated.Computer Scienc

A Comparison Study of LDPC and BCH Codes

The need for efficient and reliable digital data communication systems has been rising rapidly in recent years. There are various reasons that have brought this need for the communication systems, among them are the increase in automatic data processing equipment and the increased need for long range communication. Therefore, the LDPC and BCH codes were developed for achieving more reliable data transmission in communication systems. This project covers the research about the LDPC and BCH error correction codes. Algorithm for simulating both the LDPC and BCH codes were also being investigated, which includes generating the parity check matrix, generating the message code in Galois array matrix, encoding the message bits, modulation and decoding the message bits for LDPC. Matlab software is used for encoding and decoding the codes. The percentage of accuracy for LDPC simulation codes are ranging from 95% to 99%. The results obtained shows that the LDPC codes are more efficient and reliable than the BCH codes coding method of error correction because the LDPC codes had a channel performance very close to the Shannon limit. LDPC codes are a class of linear block codes that are proving to be the best performing forward error correction available. Markets such as broadband wireless and mobile networks operate in noisy environments and need powerful error correction in order to improve reliability and better data rates. Through LDPC and BCH codes, these systems can operate more reliably, efficiently and at higher data rates