Design and analysis of a reconfigurable discrete pin tooling system for molding of three-dimensional free-form objects

This paper presents the design and analysis of a new reconfigurable tooling for the fabrication of three-dimensional (3D) free-form objects. The proposed reconfigurable tooling system comprises a set of matrices of a closely stacked discrete elements (i.e., pins) arranged to form a cavity in which a free-form object can be molded. By reconfiguring the pins, a single tool can be used in the place of multiple tools to produce different parts with the involvement of much lesser time and cost. The structural behavior of a reconfigurable mold tool under process conditions of thermoplastic molding is studied using a finite element method (FEM) based methodology. Various factors that would affect the tool behavior are identified and their effects are analyzed to optimally design a reconfigurable mold tool for a given set of process conditions. A prototype, open reconfigurable mold tool is developed to present the feasibility of the proposed tooling system. Several case studies and sample parts are also presented in this paper

A novel architecture for a reconfigurable micro machining cell

There is a growing demand for machine tools that are specifically designed for the manufacture of micro-scale components. Such machine tools are integrated into flexible micro-manufacturing systems. Design objectives for such tools include energy efficiency, small footprint and importantly flexibility, with the ability to easily reconfigure the manufacturing system in response to process requirements and product demands. Such systems find application in medical, photonics, automotive and electronic industries. In this paper, a new architecture for a reconfigurable micro manufacturing system is presented. The proposed architecture comprises a micro manufacturing cell with the key design feature being a hexagonal-base on which three tool heads can be attached to three of its sides. Each such machine-tool head, or processing module, is able to perform a different manufacturing process. These tool heads are interchangeable, enabling the cell to be configured to process a wide range of components with different materials, dimensions, tolerances and specification. Additional components of the cell include manipulation robots and an automated buffer unit. Such cells can be integrated into a manufacturing system via a modular conveyor belt to transfer parts from one cell to another and into assembly. A key consideration of the architecture is a control system that is also modular and reconfigurable; such that when new processing modules are introduced the control system is aware of the change and adjusts accordingly. Further to this coordination, issues between modules and machining cells are also considered. Other design considerations include work-piece holding and manipulation. This paper provides an overview of the architecture, the key design and implementation challenges as well as a high level operational performance assessment by means of a discrete event simulation model of the micro factory cell

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

Design of generic modular reconfigurable platforms (GMRPS) for a product-oriented micro manufacturing system

With the proposition of the concept of product-service systems, many manufacturers are focusing on selling services or functionality rather than products. Industrial production is shifting production models from mass production to mass customization and highly personalized needs. As a result, there is a tendency for manufacturing system suppliers to develop product-oriented systems to responsively cope with the dynamic fast moving competitive market. The key features of such a manufacturing system are the reconfigurability and adaptability, which can enable the system respond to the changeable needs of customers quickly and adaptively. Therefore, one of the challenges for the micro manufacturing system provider has been the design of a reconfigurable machine platform which will provide the functionalities and flexibility required by the product-oriented systems. In this paper, a new micro manufacturing platform, i.e. a generic modular reconfigurable platform (GMRP) is proposed in order to provide an effective means for fabrication of high quality micro products at low cost in a responsive manner. The GMRP-based system aims to be a product-oriented reconfigurable, highly responsive manufacturing system particularly for high value nano/micro manufacturing purposes. To reuse components and decrease material consumption, GMRP is characterized by hybrid micro manufacturing processes, modularity of key components, and reconfigurability of machine platforms and key components. Furthermore, a practical methodology for the design of reconfigurable machine platforms is discussed against the requirements from product-driven micro manufacturing and its extension for adaptive production

Smart technologies for effective reconfiguration: the FASTER approach

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows

Subtyping for Hierarchical, Reconfigurable Petri Nets

Hierarchical Petri nets allow a more abstract view and reconfigurable Petri nets model dynamic structural adaptation. In this contribution we present the combination of reconfigurable Petri nets and hierarchical Petri nets yielding hierarchical structure for reconfigurable Petri nets. Hierarchies are established by substituting transitions by subnets. These subnets are themselves reconfigurable, so they are supplied with their own set of rules. Moreover, global rules that can be applied in all of the net, are provided

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Coarse-Grained Reconfigurable Arrays (CGRAs) enable ease of programmability and result in low development costs. They enable the ease of use specifically in reconfigurable computing applications. The smaller cost of compilation and reduced reconfiguration overhead enables them to become attractive platforms for accelerating high-performance computing applications such as image processing. The CGRAs are ASICs and therefore, expensive to produce. However, Field Programmable Gate Arrays (FPGAs) are relatively cheaper for low volume products but they are not so easily programmable. We combine best of both worlds by implementing a Virtual Coarse-Grained Reconfigurable Array (VCGRA) on FPGA. VCGRAs are a trade off between FPGA with large routing overheads and ASICs. In this perspective we present a novel heterogeneous Virtual Coarse-Grained Reconfigurable Array (VCGRA) called "Pixie" which is suitable for implementing high performance image processing applications. The proposed VCGRA contains generic processing elements and virtual channels that are described using the Hardware Description Language VHDL. Both elements have been optimized by using the parameterized configuration tool flow and result in a resource reduction of 24% for each processing elements and 82% for each virtual channels respectively.Comment: Presented at 3rd International Workshop on Overlay Architectures for FPGAs (OLAF 2017) arXiv:1704.0880

Improving reconfigurable systems reliability by combining periodical test and redundancy techniques: a case study

This paper revises and introduces to the field of reconfigurable computer systems, some traditional techniques used in the fields of fault-tolerance and testing of digital circuits. The target area is that of on-board spacecraft electronics, as this class of application is a good candidate for the use of reconfigurable computing technology. Fault tolerant strategies are used in order for the system to adapt itself to the severe conditions found in space. In addition, the paper describes some problems and possible solutions for the use of reconfigurable components, based on programmable logic, in space applications