Guaranteed passive parameterized model order reduction of the partial element equivalent circuit (PEEC) method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach

Parametric macromodeling of lossy and dispersive multiconductor transmission lines

We propose an innovative parametric macromodeling technique for lossy and dispersive multiconductor transmission lines (MTLs) that can be used for interconnect modeling. It is based on a recently developed method for the analysis of lossy and dispersive MTLs extended by using the multivariate orthonormal vector fitting (MOVF) technique to build parametric macromodels in a rational form. They take into account design parameters, such as geometrical layout or substrate features, in addition to frequency. The presented technique is suited to generate state-space models and synthesize equivalent circuits, which can be easily embedded into conventional SPICE-like solvers. Parametric macromodels allow to perform design space exploration, design optimization, and sensitivity analysis efficiently. Numerical examples validate the proposed approach in both frequency and time domain

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs

Application of Taylor models to the worst-case analysis of stripline interconnects

This paper outlines a preliminary application of Taylor models to the worst-case analysis of transmission lines with bounded uncertain parameters. Taylor models are an algebraic technique that represents uncertain quantities in terms of a Taylor expansion complemented by an interval remainder encompassing approximation and truncation errors. The Taylor model formulation is propagated from input uncertainties to output responses through a suitable redef nition of the algebraic operations involved in their calculation. While the Taylor expansion def nes an analytical and parametric model of the response, the remainder provides a conservative bound inside which the true value is guaranteed to lie. The approach is validated against the SPICE simulation of a coupled stripline and shows promising accuracy and eff ciency

Compact and accurate models of large single-wall carbon-nanotube interconnects

Single-wall carbon nanotubes (SWCNTs) have been proposed for very large scale integration interconnect applications and their modeling is carried out using the multiconductor transmission line (MTL) formulation. Their time-domain analysis has some simulation issues related to the high number of SWCNTs within each bundle, which results in a highly complex model and loss of accuracy in the case of long interconnects. In recent years, several techniques have been proposed to reduce the complexity of the model whose accuracy decreases as the interconnection length increases. This paper presents a rigorous new technique to generate accurate reduced-order models of large SWCNT interconnects. The frequency response of the MTL is computed by using the spectral form of the dyadic Green's function of the 1-D propagation problem and the model complexity is reduced using rational-model identification techniques. The proposed approach is validated by numerical results involving hundreds of SWCNTs, which confirm its capability of reducing the complexity of the model, while preserving accuracy over a wide frequency range

Near-field scanning microwave microscope for interline capacitance characterization of nanoelectronics interconnect

We have developed a noncontact method for measurement of the interline capacitance in Cu/low-k interconnect. It is based on a miniature test vehicle with net capacitance of a few femto-Farads formed by two 20-\mu m-long parallel wires (lines) with widths and spacings the same as those of the interconnect wires of interest. Each line is connected to a small test pad. The vehicle impedance is measured at 4 GHz by a near-field microwave probe with 10 \mu m probe size via capacitive coupling of the probe to the vehicle's test pads. Full 3D finite element modeling at 4 GHz confirms that the microwave radiation is concentrated between the two wires forming the vehicle. An analytical lumped element model and a short/open calibration approach have been proposed to extract the interline capacitance value from the measured data. We have validated the technique on several test vehicles made with copper and low-k dielectric on a 300 mm wafer. The vehicles interline spacing ranges from 0.09 to 1 \mu m and a copper line width is 0.15 \mu m. This is the first time a near-field scanning microwave microscope has been applied to measure the lumped element impedance of a test vehicle

A Perturbation Scheme for Passivity Verification and Enforcement of Parameterized Macromodels

This paper presents an algorithm for checking and enforcing passivity of behavioral reduced-order macromodels of LTI systems, whose frequency-domain (scattering) responses depend on external parameters. Such models, which are typically extracted from sampled input-output responses obtained from numerical solution of first-principle physical models, usually expressed as Partial Differential Equations, prove extremely useful in design flows, since they allow optimization, what-if or sensitivity analyses, and design centering. Starting from an implicit parameterization of both poles and residues of the model, as resulting from well-known model identification schemes based on the Generalized Sanathanan-Koerner iteration, we construct a parameter-dependent Skew-Hamiltonian/Hamiltonian matrix pencil. The iterative extraction of purely imaginary eigenvalues ot fhe pencil, combined with an adaptive sampling scheme in the parameter space, is able to identify all regions in the frequency-parameter plane where local passivity violations occur. Then, a singular value perturbation scheme is setup to iteratively correct the model coefficients, until all local passivity violations are eliminated. The final result is a corrected model, which is uniformly passive throughout the parameter range. Several numerical examples denomstrate the effectiveness of the proposed approach.Comment: Submitted to the IEEE Transactions on Components, Packaging and Manufacturing Technology on 13-Apr-201

Physics-based passivity-preserving parameterized model order reduction for PEEC circuit analysis

The decrease of integrated circuit feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods, and model order reduction (MOR) methods have proven to be very effective in combating such high complexity. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the circuit under study as a function of design parameters such as geometrical and substrate features. Traditional MOR techniques perform order reduction only with respect to frequency, and therefore the computation of a new electromagnetic model and the corresponding reduced model are needed each time a design parameter is modified, reducing the CPU efficiency. Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We propose a novel PMOR technique applicable to PEEC analysis which is based on a parameterization process of matrices generated by the PEEC method and the projection subspace generated by a passivity-preserving MOR method. The proposed PMOR technique guarantees overall stability and passivity of parameterized reduced order models over a user-defined range of design parameter values. Pertinent numerical examples validate the proposed PMOR approach