A Finite Element approach to understanding constitutive elasto-plastic, visco-plastic behaviour in lead free micro-electronic BGA structures

This work investigates the non-linear elasto-plastic and visco-plastic behaviour of lead free solder material and soldered joints. Specifically, Finite Element (FE) tools were used to better understand the deformations within Ball Grid Array solder joints (BGA), and numerical and analytical methods were developed to quantify the identified constituent deformations. FE material models were based on the same empirical constitutive models (elastic, plastic and creep) used in analytical calculations. The current work recognises the large number of factors influencing material behaviour which has led to a wide range of published material properties for near eutectic SnAgCu alloys. The work discovered that the deformation within the BGA was more complex than is generally assumed in the literature. It was shown that shear deformation of the solder ball could account for less than 5% of total measured displacement in BGA samples. Shear displacement and rotation of the solder balls relative to the substrate are sensitive to the substrate orthotropic properties and substrate geometry (relative to solder volume and array pattern). The FE modelling was used to derive orthotropic FR4 properties independently using published data. An elastic modulus for Sn3.8Ag0.7Cu was measured using homologous temperatures below 0.3. Suggested values of Abaqus-specific creep parameters m and f (not found in literature) for Sn3.8Ag0.7Cu have been validated with published data. Basic verification against simple analytical calculations has given a better understanding of the components of overall specimen displacement that is normally missing from empirical validation alone. A combined approach of numerical and analytical modelling of BGAs, and mechanical tests, is recommended to harmonise published work, exploit new material data and for more informed analysis of new configurationsEPSRC-funded PhD studentshi

Modelling of the reliability of flip chip lead-free solder joints at high-temperature excursions

At high-temperature operations of electronic control devices, Tin-Silver-Copper (SnAgCu) alloy solder joints used to assemble the component of the devices are functioning at homologous temperature above 0.8. In such ambient temperatures, solder alloys have limited mechanical strength and will be sensitive to strain rate. The sensitivity of solder properties to creep/visco-plastic deformation increases the rate of accumulation of plastic damage in the alloy and decreases the number of cycles to failure (Nf) of the joints. Most untimely rupture of solder joints in high-temperature electronics (HTE) system usually culminates in colossal loss of resources and lives. Typical incidences are reported in recent automotive and aircraft crashes as well as the collapse of oil-well logging equipment. To increase the mean time to failure (MTTF) of solder joints in HTE, an in-depth understanding and accurate prediction of the response of solder joints to thermally induced plastic strain damage is crucial. This study concerns the prediction of the reliability of lead-free solder joints in a flip chip (FC) model FC48D6.3C457 which is mounted on a substrate and the assembly subjected to high-temperature excursions. The research investigates the effect of the high-temperature operations on reliability of the joints. In addition, the investigation examines the impact of control factors (component stand-off height (CSH), inter-metallic compound (IMC) thickness, number of thermal cycle and solder volume) on Nf of the joints. A model developed in the course of this investigation was employed to create the assembly solder joints architecture. The development of the model and creation of the bump profile involve a combination of both analytical and construction methods. The assembled package on a printed circuit board (PCB) was subjected to accelerated temperature cycle (ATC) employing IEC standard 60749-25 in parts. The cycled temperature range is between -38 oC and 157 oC. Deformation behaviour of SnAgCu alloy solder in the joints is captured using Anand’s visco-plasticity model and the response of other materials in the assembly were simulated with appropriate model. The results demonstrate that the reliability of solder joints operating at elevated temperatures is dependent on CSH, thickness of IMC and solder volume. It also shows that incorporating the IMC layer in the geometric models significantly improves the level of accuracy of fatigue life prediction to ± 22.5% (from the ± 25% which is currently generally accepted). The findings also illustrate that the magnitude of the predicted damage and fatigue life are functions of the number of ATC employed. The extensive set of results from the modelling study has demonstrated the need for incorporating the IMC layer in the geometric model to ensure greater accuracy in the prediction of solder joint service life. The technique developed for incorporating the IMC layer will be of value to R&D engineers and scientists engaged in high-temperature applications in the automotive, aerospace and oil-well logging sectors. The results have been disseminated through peer reviewed journals and also presentations at international conferences

Thermal and thermo-mechanical performance of voided lead-free solder thermal interface materials for chip-scale packaged power device

The need to maximise thermal performance of electronic devices coupled with the continuing trends on miniaturization of electronic packages require innovative package designs for power devices and modules such as Electronic Control Unit (ECU). Chip scale packaging (CSP) technology offer promising solution for packaging power electronics. This is as a result of the technology’s relatively improved thermal performance and inherent size advantage. In CSP technology, heat removal from the device could be enhanced through the backside of the chip. Heat dissipating units such as heat spreader and/or heat sink can be attached to the backside (reverse side) of the heat generating silicon die (via TIM) in an effort to improve the surface area available for heat dissipation. TIMs are used to mechanically couple the heat generating chip to a heat sinking device and more crucially to enhance thermal transfer across the interface. Extensive review shows that solder thermal interface materials (STIMs) apparently offer better thermal performance than comparable state-of-the-art commercial polymer-based TIMs and thus a preferable choice in packaging power devices. Nonetheless, voiding remains a major reliability concern of STIMs. This is coupled with the fact that solder joints are generally prone to fatigue failures under thermal cyclic loading. Unfortunately, the occurrence of solder voids is almost unavoidable during manufacturing process and is even predominant in lead (Pb)-free solder joints. The impacts of these voids on the thermal and mechanical performance of solder joints are not clearly understood and scarcely available in literature especially with regards to STIMs (large area solder joints). Hence, this work aims to investigate STIM and the influence of voids on the thermo-mechanical and thermal performance of STIM. As previous results suggest that factors such as the location, configuration (spatial arrangement) and size of voids play vital roles on the exact effect of voids, extensive three dimensional (3D) finite element modelling is employed to elucidate the precise effect of these void features on a Pb-free STIM selected after thermo-mechanical fatigue test of standard Pb-free solder alloys. Finite element analysis (FEA) results show that solder voids configuration, size and location are all vital parameters in evaluating the mechanical and thermal impacts of voids. Depending on the location, configuration and size of voids; solder voids can either influence the initiation or propagation of damage in the STIM layer or the location of hot spot on the heat generating chip. Experimental techniques are further employed to compare and correlate levels of voiding and shear strength for representative Pb-free solders. Experimental results also suggest that void size, location and configuration may have an influence on the mechanical durability of solder joints. The findings of this research work would be of interest to electronic packaging engineers especially in the automotive sector and have been disseminated through publications in peer reviewed journals and presentations in international conferences

Development of a Rapid Fatigue Life Testing Method for Reliability Assessment of Flip-Chip Solder Interconnects

The underlying physics of failure are critical in assessing the long term reliability of power packages in their intended field applications, yet traditional reliability determination methods are largely inadequate when considering thermomechanical failures. With current reliability determination methods, long test durations, high costs, and a conglomerate of concurrent reliability degrading threat factors make effective understanding of device reliability difficult and expensive. In this work, an alternative reliability testing apparatus and associated protocol was developed to address these concerns; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. Two test stands were fabricated to evaluate device reliability at high frequency (60 cycles/minute) with the first being a single-directional unit capable of exerting large forces (up to 20 N) on solder interconnects in one direction. The second test stand was developed to allow for bi-directional application of stress and the integration of an oven to enable testing at elevated steady-state temperatures. Given the high frequency of testing, elevated temperatures are used to emulate the effects of creep on solder fatigue lifetime. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using resistance monitoring techniques to detect the number of cycles-to-failure (CTF). Resistance monitoring was performed using specially designed and fabricated, device analogous test vehicles assembled with the ability to monitor circuit resistance in situ. When a resistance rise of 30 % was recorded, the device was said to have failed. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke’s Law for springs and damage deflection to accurately assess the mechanical strength of tested devices

Analysis of column interconnects for wafer level packages

Master'sMASTER OF ENGINEERIN

Carbon nanotubes for thermal interface materials in microelectronic packaging

As the integration scale of transistors/devices in a chip/system keeps increasing, effective cooling has become more and more important in microelectronics. To address the thermal dissipation issue, one important solution is to develop thermal interface materials with higher performance. Carbon nanotubes, given their high intrinsic thermal and mechanical properties, and their high thermal and chemical stabilities, have received extensive attention from both academia and industry as a candidate for high-performance thermal interface materials. The thesis is devoted to addressing some challenges related to the potential application of carbon nanotubes as thermal interface materials in microelectronics. These challenges include: 1) controlled synthesis of vertically aligned carbon nanotubes on various bulk substrates via chemical vapor deposition and the fundamental understanding involved; 2) development of a scalable annealing process to improve the intrinsic properties of synthesized carbon nanotubes; 3) development of a state-of-art assembling process to effectively implement high-quality vertically aligned carbon nanotubes into a flip-chip assembly; 4) a reliable thermal measurement of intrinsic thermal transport property of vertically aligned carbon nanotube films; 5) improvement of interfacial thermal transport between carbon nanotubes and other materials. The major achievements are summarized. 1. Based on the fundamental understanding of catalytic chemical vapor deposition processes and the growth mechanism of carbon nanotube, fast synthesis of high-quality vertically aligned carbon nanotubes on various bulk substrates (e.g., copper, quartz, silicon, aluminum oxide, etc.) has been successfully achieved. The synthesis of vertically aligned carbon nanotubes on the bulk copper substrate by the thermal chemical vapor deposition process has set a world record. In order to functionalize the synthesized carbon nanotubes while maintaining their good vertical alignment, an in situ functionalization process has for the first time been demonstrated. The in situ functionalization renders the vertically aligned carbon nanotubes a proper chemical reactivity for forming chemical bonding with other substrate materials such as gold and silicon. 2. An ultrafast microwave annealing process has been developed to reduce the defect density in vertically aligned carbon nanotubes. Raman and thermogravimetric analyses have shown a distinct defect reduction in the CNTs annealed in microwave for 3 min. Fibers spun from the as-annealed CNTs, in comparison with those from the pristine CNTs, show increases of ~35% and ~65%, respectively, in tensile strength (~0.8 GPa) and modulus (~90 GPa) during tensile testing; an ~20% improvement in electrical conductivity (~80000 S m⁻¹) was also reported. The mechanism of the microwave response of CNTs was discussed. Such an microwave annealing process has been extended to the preparation of reduced graphene oxide. 3. Based on the fundamental understanding of interfacial thermal transport and surface chemistry of metals and carbon nanotubes, two major transfer/assembling processes have been developed: molecular bonding and metal bonding. Effective improvement of the interfacial thermal transport has been achieved by the interfacial bonding. 4. The thermal diffusivity of vertically aligned carbon nanotube (VACNT, multi-walled) films was measured by a laser flash technique, and shown to be ~30 mm² s⁻¹ along the tube-alignment direction. The calculated thermal conductivities of the VACNT film and the individual CNTs are ~27 and ~540 W m⁻¹ K⁻¹, respectively. The technique was verified to be reliable although a proper sampling procedure is critical. A systematic parametric study of the effects of defects, buckling, tip-to-tip contacts, packing density, and tube-tube interaction on the thermal diffusivity was carried out. Defects and buckling decreased the thermal diffusivity dramatically. An increased packing density was beneficial in increasing the collective thermal conductivity of the VACNT film; however, the increased tube-tube interaction in dense VACNT films decreased the thermal conductivity of the individual CNTs. The tip-to-tip contact resistance was shown to be ~1×10⁻⁷ m² K W⁻¹. The study will shed light on the potential application of VACNTs as thermal interface materials in microelectronic packaging. 5. A combined process of in situ functionalization and microwave curing has been developed to effective enhance the interface between carbon nanotubes and the epoxy matrix. Effective medium theory has been used to analyze the interfacial thermal resistance between carbon nanotubes and polymer matrix, and that between graphite nanoplatlets and polymer matrix.PhDCommittee Chair: Wong, C. P.; Committee Member: Graham, Samuel; Committee Member: Hess, Dennis; Committee Member: Jacob, Karl; Committee Member: Wang, Z. L.; Committee Member: Yao, Don

Lebensdauervorhersage für (SnAgCu- und SnPb-) aufgelötete Leistungshalbleiter mittels primärem und sekundärem Kriechen

The objective of this thesis was to accurately check and improve the models existing for eutectic solder alloys used in simulation tools. Creep deformation,which is the most important deformation mode of solders, of two solder alloys, the widely used eutectic SnPb and the environmentally friendly alternative solder alloy SnAgCu was tested. It was shown that it is necessary to model two different stages of this high temperature induced mechanism: To improve the current material definition, primary creep must be implemented in the FE-software in addition to the existing secondary creep models. This thesis shows how it is possible to test creep behaviour under cyclic loading conditions with a test specimen of novel design. So, primary creep was observed and reoccurs cyclically under such test conditions. Furthermore, steady state creep is also always observed. A Constitutive equation combining both primary and secondary creep was given and verified. This model was implemented in FE-code Ansys, and after performing different kinds of simulation, the necessity of simulating primary creep was demonstrated. In order to achieve reliability information by FE-simulation of solder die attach, the creep-fatigue behaviour with the mean of crack propagation must be modeled. Various kinds of chips on copper substrate (power-transistors) were thermally tested, and different methods were used to investigate crack propagation. These methods were scanning acoustic microscopy and microstructure analysis by optical microscopy. The influence of damage on thermal behaviour (i.e. the thermal resistance of the device) was also assessed. These results were compared with the simulation results in order to build a lifetime prediction model based on crack propagation analysis.Das Ziel dieser Arbeit war es, die schon vorhandenen Modelle für die Lötstellensimulation zu verbessern. Da das Kriechen für die Verformung von Lötlegierungen der wichtigste Mechanismus ist, wurde das Kriechverhalten für zwei Lötlegierungen untersucht. Es handelt sich dabei um die weltweit bekannten Legierungen eut. SnPb und das umweltverträglichere SnAgCu. Es ist empfehlenswert zwei Bereiche dieses Hoch-Temperatur Mechanismus zu modellieren. Um die bisherigen Werkstoffsmodelle verbessern zu können, ist das primäre Kriechen zusätzlich zu den bestehenden sekundären Kriechmodellen in FE-Programme zu implementieren. Diese Arbeit zeigt, wie das Kriechen unter zyklischer Belastung mit einer neuen Prüfkörpergeometrie untersucht werden kann. Unter solchen Randbedingungen ist erneut primäres Kriechen zu beobachten. Weiterhin wurde immer auch stationäres Kriechen beobachtet. Eine Zustandsgleichung, bestehend aus primärem und sekundärem Kriechen, wurde entwickelt. Dieses Modell wurde in den FE-Code Ansys implementiert, und nach der Durchführung von verschiedenen Packagingsimulationen wurde ebenfalls festgestellt, das das primäre Kriechen unbedingt berücksichtigt werden muss. Um eine Lebensdauerprognose von flächigen Lötstellen zu erreichen, müssen die Kriechermüdung sowie der Rissfortschritt modelliert werden. Einige Testdemonstratoren (Leistungstransistor auf Kupfer) wurden thermo-mechanisch geprüft (Temperaturschock und Temperaturwechsel). Durch zwei verschiedene Methoden (Ultraschallmikroskopie und Gefügeanalyse) wurde die Rissinitiierung und der Rissforschritt untersucht. Der Einfluss der Schädigung auf das thermische Verhalten des Testobjektes (thermischer Widerstand des Bauelements) wurde ebenfalls bewertet. Diese experimentellen Ergebnisse wurden mit den Simulationsergebnissen verglichen, um ein neues Lebensdauermodell basierend auf der Rissfortschrittanalyse zu bauen. Eine sehr gute Übereinstimmung erlaubt nun die Zuverlässigkeitsvorhersage von flächig aufgelöteten Chips im Bereich der Leistungselektronik