Parametric Design Synthesis of Distributed Embedded Systems

This paper presents a design synthesis method for distributed embedded systems. In such systems, computations can flow through long pipelines of interacting software components, hosted on a variety of resources, each of which is managed by a local scheduler. Our method automatically calibrates the local resource schedulers to achieve the system's global end-to-end performance requirements. A system is modeled as a set of distributed task chains (or pipelines), where each task represents an activity requiring nonzero load from some CPU or network resource. Task load requirements can vary stochastically, due to second-order effects like cache memory behavior, DMA interference, pipeline stalls, bus arbitration delays, transient head-of-line blocking, etc. We aggregate these effects -- along with a task's per-service load demand -- and model them via a single random variable, ranging over an arbitrary discrete probability distribution. Load models can be obtained via profiling tasks in isolation, or simply by using an engineer's hypothesis about the system's projected behavior. The end-to-end performance requirements are posited in terms of throughput and delay constraints. Specifically, a pipeline's delay constraint is an upper bound on the total latency a computatation can accumulate, from input to output. The corresponding throughput constraint mandates the pipeline's minimum acceptable output rate -- counting only outputs which meet their delay constraints. Since per-component loads can be generally distributed, and since resources host stages from multiple pipelines, meeting all of the system's end-to-end constraints is a nontrivial problem. Our approach involves solving two sub-problems in tandem: (A)~finding an optimal proportion of load to allocate each task and channel; and (B)~deriving the best combination of service intervals over which all load proportions can be guaranteed. The design algorithms use analytic approximations to quickly estimate output rates and propagation delays for candidate solutions. When all parameters are synthesized, the estimated end-to-end performance metrics are re-checked by simulation. The per-component load reservations can then be increased, with the synthesis algorithms re-run to improve performance. At that point the system can be configured according to the synthesized scheduling parameters -- and then re-validated via on-line profiling. In this paper we demonstrate our technique on an example system, and compare the estimated performance to its simulated on-line behavior. (Also cross-referenced as UMIACS-TR-98-18

Formal Model Engineering for Embedded Systems Using Real-Time Maude

This paper motivates why Real-Time Maude should be well suited to provide a formal semantics and formal analysis capabilities to modeling languages for embedded systems. One can then use the code generation facilities of the tools for the modeling languages to automatically synthesize Real-Time Maude verification models from design models, enabling a formal model engineering process that combines the convenience of modeling using an informal but intuitive modeling language with formal verification. We give a brief overview six fairly different modeling formalisms for which Real-Time Maude has provided the formal semantics and (possibly) formal analysis. These models include behavioral subsets of the avionics modeling standard AADL, Ptolemy II discrete-event models, two EMF-based timed model transformation systems, and a modeling language for handset software.Comment: In Proceedings AMMSE 2011, arXiv:1106.596

Sound and Automated Synthesis of Digital Stabilizing Controllers for Continuous Plants

Modern control is implemented with digital microcontrollers, embedded within a dynamical plant that represents physical components. We present a new algorithm based on counter-example guided inductive synthesis that automates the design of digital controllers that are correct by construction. The synthesis result is sound with respect to the complete range of approximations, including time discretization, quantization effects, and finite-precision arithmetic and its rounding errors. We have implemented our new algorithm in a tool called DSSynth, and are able to automatically generate stable controllers for a set of intricate plant models taken from the literature within minutes.Comment: 10 page

Learning dispositif and emotional attachment:a preliminary international investigation

This research investigated the significance of learning dispositif (LD) and emotional attachment (EA) on perceived learning success (LS) across a diaspora of Western, Russian, Asian, Middle Eastern and Chinese student cohorts. Foucault’s LD captures the disparate socio-cultural contexts, institutional milieus and more or less didactic teaching styles that moderate learning. EA is a multi-dimensional notion involving affective bonds that emerged in child psychology and spread to marketing and other fields. The sequential explanatory research reviewed the learning and EA literatures and generated an LD–EA framework to structure the quantitative phase of its mixed investigations. In 2017 and 2018, the research collected 150 responses and used a range of statistical techniques for quantitative analysis. It found that LS varied significantly across cohorts, intimating that dispositifs influence learning. Nonparametric analysis suggested that EA also influenced learning, but regressions were inconclusive. Exploratory techniques hint at a dynamic mix of emotional or cognitive motivations during the student learning journey, involving structural breaks in student/instructor relationships. Cluster analysis identified distinct student groupings, linked to years of learning. Separately, qualitative analysis of open-ended survey questions and expert interviews intimates that frequent teacher interactions can increase EA. The synthesis of quantitative with qualitative results and pedagogical reflection suggests that LD and EA both influence learning in a complex, dynamic system. The key constituents for EA are Affection, Connection, Social Presence (SP), Teaching Presence (TP) and Flow but student emotional engagement is conditioned by the socio-cultural milieu (LD) and associated factors like relationships and trust. Unlike in the Community of Learning framework, in the EA framework Cognitive Presence (CP) is an outcome of the interaction between these EA constituents, associated factors and the socio-cultural milieu. Finally, whilst awareness of culture and emotions is a useful pedagogical consideration, learning mainstays remain inclusive educational systems that identify student needs and support well-designed programmes. Within these, scaffolded modules should include a variety of engaging learning activities with non-threatening formative and trustworthy summative feedback. We acknowledge some statistical study limitations, but its tentative findings make a useful preliminary contribution

Parametric, Secure and Compact Implementation of RSA on FPGA

We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated block multipliers as the main functional unit and Block-RAM as storage unit for the operands. The adopted design methodology allows adjusting the number of multipliers, the radix used in the multipliers, and number of words to meet the system requirements such as available resources, precision and timing constraints. The architecture, based on the Montgomery modular multiplication algorithm, utilizes a pipelining technique that allows concurrent operation of hardwired multipliers. Our design completes 1020-bit and 2040-bit modular multiplications in 7.62 μs and 27.0 μs, respectively. The multiplier uses a moderate amount of system resources while achieving the best area-time product in literature. 2040-bit modular exponentiation engine can easily fit into Xilinx Spartan-3E 500; moreover the exponentiation circuit withstands known side channel attacks

Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies