Cerium oxide based resistive random access memory devices

Resistive Random Access Memory (RRAM) is an emerging technology of non-volatile memory (NVM). Although the observation of metal oxide that can undergo an abrupt insulator-metal transition into a conductive state has been known for over 40 years, researchers started investigating those materials for memory applications in late 1990s. It has been considered as the next generation memory technology to replace current flash memory because RRAM has demonstrated feasible switching characteristics and potential to build high density arrays and also RRAM is also compatible with contemporary CMOS processes, which means RRAM can be integrated into current CMOS chips. While the structure of RRAM is a simple metal-insulator-metal (MIM) device, there are numerous materials that exhibit resistive switching. The switching behavior is not only dependent on the switching layer materials but also dependent on the choice of metal electrodes and their interfacial properties. Many metal oxides such as hafnium oxide, titanium oxide, aluminum oxide, nickel oxide (NiO), tantalum oxide and etc. have been studied in details; however, some materials are unexplored such as cerium oxide. In addition to nonvolatile storage applications, RRAM is considered as one of essential elements for advancing neuromorphic computing because of its analog switching and retention characteristics. This thesis investigated CeO[subscript x]-based RRAMs, from its fundamental device characteristics to neuromorphic applications.Electrical and Computer Engineerin

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Variability estimation in resistive switching devices, a numerical and kinetic Monte Carlo perspective

Acknowledgments The authors thank the support of the Spanish Ministry of Science, Innovation and Universities and the FEDER program through projects TEC2017-84321-C4-1-R, TEC2017-84321-C4-3-R, and projects A.TIC.117.UGR18, IE2017-5414 and B.TIC.624.UGR20 funded by the Consejería de Conocimiento, Investigación y Universidad, Junta de Andalucía (Spain) and the FEDER program. Funding for open access charge: Universidad de Granada/CBUAWe have analyzed variability in resistive memories (Resistive Random Access Memories, RRAMs) making use of advanced numerical techniques to process experimental measurements and simulations based on the kinetic Monte Carlo technique. The devices employed in the study were fabricated using the TiN/Ti/HfO2/W stack. The switching parameters were obtained making use of new developed extraction methods. The appropriateness of the advanced parameter extraction methodologies has been checked by comparison to kinetic Monte Carlo simulations; in particular, the reset and set events have been studied and detected. The data obtained were employed to shed light on the resistive switching operation and the cycle-to-cycle variability. It has been shown that variability depends on the numerical technique employed to obtain the set and reset voltages, therefore, this issue must be taken into consideration in RS characterization and modeling studies. The proposed techniques are complementary and depending on the technology and the curves shape the features of a particular method could make it to be the most appropriate.Spanish Ministry of Science, Innovation and Universities and the FEDER program through projects TEC2017-84321-C4-1-R, TEC2017-84321-C4-3-RConsejería de Conocimiento, Investigación y Universidad, Junta de Andalucía (Spain) and the FEDER program, projects A.TIC.117.UGR18, IE2017-5414 and B.TIC.624.UGR20Funding for open access charge: Universidad de Granada/CBU

Parameter extraction techniques for the analysis and modeling of resistive memories

A revision of the different numerical techniques employed to extract resistive switching (RS) and modeling parameters is presented. The set and reset voltages, commonly used for variability estimation, are calculated for different resistive memory technologies. The methodologies to extract the series resistance and the parameters linked to the charge-flux memristive modeling approach are also described. It is found that the obtained cycle-to-cycle (C2C) variability depends on the numerical technique used. This result is important, and it implies that when analyzing C2C variability, the extraction technique should be described to perform fair comparisons between different resistive memory technologies. In addition to the use of extensive experimental data for different types of resistive memories, we have also included kinetic Monte Carlo (kMC) simulations to study the formation and rupture events of the percolation paths that constitute the conductive filaments (CF) that allow resistive switching operation in filamentary unipolar and bipolar devices.Consejería de Conocimiento, Investigaci ́on y Universidad, Junta de Andalucía (Spain) and the FEDER program for the projects A.TIC.117.UGR18, B-TIC-624-UGR20 and IE2017-5414Ramón y Cajal grant No. RYC2020-030150-IFunding for open access charge: Universidad de Granada/CBU

Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

Producción CientíficaLogic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.European Union’s Horizon 2020 Research and Innovation Programme under Grant 64863

Multiscale modeling for application-oriented optimization of resistive random-access memory

Memristor-based neuromorphic systems have been proposed as a promising alternative to von Neumann computing architectures, which are currently challenged by the ever-increasing computational power required by modern artificial intelligence (AI) algorithms. The design and optimization of memristive devices for specific AI applications is thus of paramount importance, but still extremely complex, as many dierent physical mechanisms and their interactions have to be accounted for, which are, in many cases, not fully understood. The high complexity of the physical mechanisms involved and their partial comprehension are currently hampering the development of memristive devices and preventing their optimization. In this work, we tackle the application-oriented optimization of Resistive Random-Access Memory (RRAM) devices using a multiscale modeling platform. The considered platform includes all the involved physical mechanisms (i.e., charge transport and trapping, and ion generation, diusion, and recombination) and accounts for the 3D electric and temperature field in the device. Thanks to its multiscale nature, the modeling platform allows RRAM devices to be simulated and the microscopic physical mechanisms involved to be investigated, the device performance to be connected to the material's microscopic properties and geometries, the device electrical characteristics to be predicted, the effect of the forming conditions (i.e., temperature, compliance current, and voltage stress) on the device's performance and variability to be evaluated, the analog resistance switching to be optimized, and the device's reliability and failure causes to be investigated. The discussion of the presented simulation results provides useful insights for supporting the application-oriented optimization of RRAM technology according to specific AI applications, for the implementation of either non-volatile memories, deep neural networks, or spiking neural networks

Microscopic origin of random telegraph noise fluctuations in aggressively scaled RRAM and its impact on read disturb variability

Random telegraph noise (RTN) is an important intrinsic phenomenon of any logic or memory device that is indicative of the reliability and stochastic variability in its performance. In the context of the resistive random access memory (RRAM), RTN becomes a key criterion that determines the read disturb immunity and memory window between the low (LRS) and high resistance states (HRS). With the drive towards ultra-low power memory (low reset current) and aggressive scaling to 10 × 10 nm2 area, contribution of RTN is significantly enhanced by every trap (vacancy) in the dielectric. The underlying mechanisms governing RTN in RRAM are yet to be fully understood. In this study, we aim to decode the role of conductance fluctuations caused by oxygen vacancy transport and inelastic electron trapping and detrapping processes. The influence of resistance state (LRS, shallow and deep HRS), reset depth and reset stop voltage (VRESET-STOP) on the conductance variability is also investigated. © 2013 IEEE

An experimental and simulation study of the role of thermal effects on variability in TiN/Ti/HfO2/W resistive switching nonlinear devices

An in-depth simulation and experimental study has been performed to analyze thermal effects on the variability of resistive memories. Kinetic Monte Carlo (kMC) simulations, that reproduce well the nonlinearity and stochasticity of resistive switching devices, have been employed to explain the experimental results. The series resistance and the transition voltages and currents have been extracted from devices based on the TiN/Ti/HfO2/W stack we have fabricated and measured at temperatures ranging from 77 K to 350 K. We observed that the variability for all the magnitudes analyzed was much higher at low temperatures. In the kMC simulations, we obtained conductive filaments (CFs) with less compactness at low temperatures. This led us to explain the higher variability, based on the variations of the CF morphology and density seen at low temperatures