Hardware for Memristive Neuromorphic Systems with Reliable Programming and Online Learning

Alternative computing technologies are highly sought after due to limitations on transistor fabrication improvements. Fabricated memristive technology allows for a non-volatile analog memory for neuromorphic computing. In an integrated CMOS process, the synapse circuits designed for a spiking neuromorphic system can use memristors to regulate accumulation in the neuron circuits. Testing the fabricated memristive devices composed of hafnium oxide and developing a model to represent the key device characteristics lead to specific design choices in implementing the analog memory core of the synapse circuit. The circuits I designed for neuromorphic computing in this process take advantage of the unique capabilities of the memristive device to store a programmable analog memory reliably and efficiently. I designed the peripheral circuitry required including the circuits for programming the memristor and for online learning capabilities

Precise Characterization and Multiobjective Optimization of Low Noise Amplifiers

Although practically all function blocks of the satellite navigation receivers are realized using the CMOS digital integrated circuits, it is appropriate to create a separate low noise antenna preamplifier based on a low noise pHEMT. Such an RF front end can be strongly optimized to attain a suitable tradeoff between the noise figure and transducer power gain. Further, as all the four principal navigation systems (GPS, GLONASS, Galileo, and COMPASS) work in similar frequency bands (roughly from 1.1 to 1.7 GHz), it is reasonable to create the low noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multiobjective optimization. A substantial improvement of a standard optimization method is also outlined to satisfy a uniform coverage of Pareto front. Moreover, for enhancing efficiency of many times repeated solutions of large linear systems during the optimization, a new modification of the Markowitz criterion is suggested compatible with fast modes of the LU factorization. Extraordinary attention was also given to the accuracy of modeling. First, an extraction of pHEMT model parameters was performed including its noise part, and several models were compared. The extraction was carried out by an original identification procedure based on a combination of metaheuristic and direct methods. Second, the equations of the passive elements (including transmission lines and T-splitters) were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Third, an optimal selection of the operating point and essential passive elements was performed using the improved optimization method. Finally, the s-parameters and noise figure of the amplifier were measured, and stability and third-order intermodulation products were also checked

Automatic design of analogue circuits

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Evolvable Hardware (EHW) is a promising area in electronics today. Evolutionary Algorithms (EA), together with a circuit simulation tool or real hardware, automatically designs a circuit for a given problem. The circuits evolved may have unconventional designs and be less dependent on the personal knowledge of a designer. Nowadays, EA are represented by Genetic Algorithms (GA), Genetic Programming (GP) and Evolutionary Strategy (ES). While GA is definitely the most popular tool, GP has rapidly developed in recent years and is notable by its outstanding results. However, to date the use of ES for analogue circuit synthesis has been limited to a few applications. This work is devoted to exploring the potential of ES to create novel analogue designs. The narrative of the thesis starts with a framework of an ES-based system generating simple circuits, such as low pass filters. Then it continues with a step-by-step progression to increasingly sophisticated designs that require additional strength from the system. Finally, it describes the modernization of the system using novel techniques that enable the synthesis of complex multi-pin circuits that are newly evolved. It has been discovered that ES has strong power to synthesize analogue circuits. The circuits evolved in the first part of the thesis exceed similar results made previously using other techniques in a component economy, in the better functioning of the evolved circuits and in the computing power spent to reach the results. The target circuits for evolution in the second half are chosen by the author to challenge the capability of the developed system. By functioning, they do not belong to the conventional analogue domain but to applications that are usually adopted by digital circuits. To solve the design tasks, the system has been gradually developed to support the ability of evolving increasingly complex circuits. As a final result, a state-of-the-art ES-based system has been developed that possesses a novel mutation paradigm, with an ability to create, store and reuse substructures, to adapt the mutation, selection parameters and population size, utilize automatic incremental evolution and use the power of parallel computing. It has been discovered that with the ability to synthesis the most up-to-date multi-pin complex analogue circuits that have ever been automatically synthesized before, the system is capable of synthesizing circuits that are problematic for conventional design with application domains that lay beyond the conventional application domain for analogue circuits

Accelerated neuromorphic cybernetics

Accelerated mixed-signal neuromorphic hardware refers to electronic systems that emulate electrophysiological aspects of biological nervous systems in analog voltages and currents in an accelerated manner. While the functional spectrum of these systems already includes many observed neuronal capabilities, such as learning or classification, some areas remain largely unexplored. In particular, this concerns cybernetic scenarios in which nervous systems engage in closed interaction with their bodies and environments. Since the control of behavior and movement in animals is both the purpose and the cause of the development of nervous systems, such processes are, however, of essential importance in nature. Besides the design of neuromorphic circuit- and system components, the main focus of this work is therefore the construction and analysis of accelerated neuromorphic agents that are integrated into cybernetic chains of action. These agents are, on the one hand, an accelerated mechanical robot, on the other hand, an accelerated virtual insect. In both cases, the sensory organs and actuators of their artificial bodies are derived from the neurophysiology of the biological prototypes and are reproduced as faithfully as possible. In addition, each of the two biomimetic organisms is subjected to evolutionary optimization, which illustrates the advantages of accelerated neuromorphic nervous systems through significant time savings

A methodology for automated design and implementation of complex analog and digital CMOS integrated circuits applying a genetic algorithm and a CAD tool for multiobjective optimization.

Tesis (Doctorado en Ciencias Naturales para el Desarrollo) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2014.This dissertation proposes an automated methodology to design and optimize electronic integrated circuits, something that could be called simulation-driven optimization. The concept of Pareto optimality or the so called Pareto front is introduced as a useful analysis tool in order to explore the design space of such circuits. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Since the problem at hand is inherently a multi-objective optimization task, many different performance measures of the circuits must be able to be easily defined and computed as fitness functions. The methodology has been validated through measurements of several fabricated test cases, using MOSIS fabrication services for a standard 0.5m CMOS technology.Instituto Tecnológico de Costa Rica. Escuela de Ingeniería Electrónica