62,308 research outputs found

    Constraints on the uncertainties of entangled symmetric qubits

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    We derive necessary and sufficient inseparability conditions imposed on the variance matrix of symmetric qubits. These constraints are identified by examining a structural parallelism between continuous variable states and two qubit states. Pairwise entangled symmetric multiqubit states are shown here to obey these constraints. We also bring out an elegant local invariant structure exhibited by our constraints.Comment: 5 pages, REVTEX, Improved presentation; Theorem on neccessary and sufficient condition included; To appear in Phys. Lett.

    Adaptive BDDC in Three Dimensions

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    The adaptive BDDC method is extended to the selection of face constraints in three dimensions. A new implementation of the BDDC method is presented based on a global formulation without an explicit coarse problem, with massive parallelism provided by a multifrontal solver. Constraints are implemented by a projection and sparsity of the projected operator is preserved by a generalized change of variables. The effectiveness of the method is illustrated on several engineering problems.Comment: 28 pages, 9 figures, 9 table

    Exact and heuristic allocation of multi-kernel applications to multi-FPGA platforms

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    FPGA-based accelerators demonstrated high energy efficiency compared to GPUs and CPUs. However, single FPGA designs may not achieve sufficient task parallelism. In this work, we optimize the mapping of high-performance multi-kernel applications, like Convolutional Neural Networks, to multi-FPGA platforms. First, we formulate the system level optimization problem, choosing within a huge design space the parallelism and number of compute units for each kernel in the pipeline. Then we solve it using a combination of Geometric Programming, producing the optimum performance solution given resource and DRAM bandwidth constraints, and a heuristic allocator of the compute units on the FPGA cluster.Peer ReviewedPostprint (author's final draft

    Beta reduction constraints

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    The constraint language for lambda structures (CLLS) can model lambda terms that are known only partially. In this paper, we introduce beta reduction constraints to describe beta reduction steps between partially known lambda terms. We show that beta reduction constraints can be expressed in an extension of CLLS by group parallelism. We then extend a known semi-decision procedure for CLLS to also deal with group parallelism and thus with beta-reduction constraints

    Processing Gapping: Parallelism and Grammatical Constraints

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    This study aims to test two hypotheses about the online processing of Gapping: whether the parser inserts an ellipsis site in an incremental fashion in certain coordinated structures (the Incremental Ellipsis Hypothesis), or whether ellipsis is a late and dispreferred option (the Ellipsis as a Last Resort Hypothesis). We employ two offline acceptability rating experiments and a sentence fragment completion experiment to investigate to what extent the distribution of Gapping is controlled by grammatical and extra-grammatical constraints. Furthermore, an eye-tracking while reading experiment demonstrated that the parser inserts an ellipsis site incrementally but only when grammatical and extra-grammatical constraints allow for the insertion of the ellipsis site. This study shows that incremental building of the Gapping structure follows from the parser’s general preference to keep the structure of the two conjuncts maximally parallel in a coordination structure as well as from grammatical restrictions on the distribution of Gapping such as the Coordination Constraint

    High-level synthesis under I/O Timing and Memory constraints

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    The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm

    Processing gapping: Parallelism and grammatical constraints

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    This study aims to test two hypotheses about the online processing of Gapping: whether the parser inserts an ellipsis site in an incremental fashion in certain coordinated structures (the Incremental Ellipsis Hypothesis), or whether ellipsis is a late and dispreferred option (the Ellipsis as a Last Resort Hypothesis). We employ two offline acceptability rating experiments and a sentence fragment completion experiment to investigate to what extent the distribution of Gapping is controlled by grammatical and extra-grammatical constraints. Furthermore, an eye-tracking while reading experiment demonstrated that the parser inserts an ellipsis site incrementally but only when grammatical and extra- grammatical constraints allow for the insertion of the ellipsis site. This study shows that incremental building of the Gapping structure follows from the parser’s general preference to keep the structure of the two conjuncts maximally parallel in a coordination structure as well as from grammatical restrictions on the distribution of Gapping such as the Coordination Constraint

    VP-Ellipsis is not licensed by VP-Topicalization

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    Starting from the observation that the constraints on VP-ellipsis (VPE) closely match those on VP-topicalization (VPT), Johnson (2001) proposes a movement account for VPE: in order for a VP to be deleted, it must first undergo topicalization. We show that although this proposal is attractive, making VPE dependent on VPT is problematic because VPE and VPT are not distributionally equivalent. While VPT targets the left periphery and consequently is subject to constraints on movement, VPE is not so restricted. We outline some alternatives for capturing the observed parallelism in the licensing of VPT and VPE
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