Energy-Efficient Wireless Interconnect Design for Non-Destructive Testing (NDT) Applications

A method for non-destructive, wireless testing of integrated circuits(ICs) is presented in this thesis. This system is suitable for applications which require testing after the manufacturing of ICs. According to Moore\u27s Law the number of transistors in an IC doubles every two years, the current probing equipment will also have to reduce its size accordingly which will be difficult after a certain point. The proposed system relies on near field communication in order to transfer data between probe and device under test. The probe and IC will include small antenna and a transceiver circuit. The antenna and the transceiver circuit can be integrated into the device without affecting the real estate and performance. Major advantages of non-destructive probing include no damage to the pads of test chip, higher test frequencies and less maintenance which will lead to higher pin densities. The antenna and transceiver circuit to be incorporated on the test chip are completely CMOS compliant.;The presented system here is a prototype which consists of a transceiver circuit along with an ultra-wideband antenna. The system was implemented in IBM 180nm CMOS process. The transceiver circuit communicates at a high frequency of 21.5GHz which in turn reduces the area consumed by the antenna and the transceiver circuit. The results obtained for our system show that an energy efficient wireless interconnect has been successfully implemented for future non-destructive testing applications

Analysis of Impact of Transformer Coupled Input Matching on Concurrent Dual-Band Low Noise Amplifier

Emerging advancements in telecommunication system need robust radio devices which can capable of working multiple frequency bands seamlessly. In any Radio Frequency (RF) receiver architecture, Low Noise Amplifier (LNA) is the mandatory front-end part in which takes place in between antenna and mixer. To support multiple frequency bands with single hardware, concurrent LNA is the more preferred topologies among others. As LNA is the very front end level of receiver, Input matching, Noise Figure (NF) and gain are the major performance parameters to be concerned. In this work, the impact of transformer coupled input matching on concurrent dual-band LNA is analyzed and verified. A concurrent LNA with concurrent matching without transformer coupling is used for comparison. A transformer coupled input matching is proposed for tunable concurrent dual-band LNA. All the circuits are implemented in UMC 180nm CMOS technology, and simulated using Cadence SpectreRF simulation tool

Analysis and Design of Wideband Low Noise Amplifier with Digital Control

The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply

The optimization of amplifiers for UWB applications

Optimizations of 0.18 μm and 0.5 μm MOSFET amplifiers without using inductors for UWB applications are presented. A 3 dB bandwidth from 3.1 GHz to 9.9 GHz with minimum 9.6 dB of transducer gain at 10.6 GHz and approximate 92.8 mWatts of total power consumption are achieved. The source and load impedances were 50 ohms. Also, the number of capacitors and resistors has been minimized. To predict characteristics more precisely, the pad capacitance is added to the output port. In addition, a different feedback topology is presented which gives a lower Noise Figure with maximum 7.73 dB at 10.6 GHz with 300 ohms feedback resistance

A 0.18µm CMOS UWB wireless transceiver for medical sensing applications

Recently, there is a new trend of demand of a biomedical device that can continuously monitor patient’s vital life index such as heart rate variability (HRV) and respiration rate. This desired device would be compact, wearable, wireless, networkable and low-power to enable proactive home monitoring of vital signs. This device should have a radar sensor portion and a wireless communication link all integrated in one small set. The promising technology that can satisfy these requirements is the impulse radio based Ultra-wideband (IR-UWB) technology. Since Federal Communications Commission (FCC) released the 3.1GHz-10.6GHz frequency band for UWB applications in 2002 [1], IR-UWB has received significant attention for applications in target positioning and wireless communications. IR-UWB employs extremely narrow Gaussian monocycle pulses or any other forms of short RF pulses to represent information. In this project, an integrated wireless UWB transceiver for the 3.1GHz-10.6GHz IR-UWB medical sensor was developed in the 0.18µm CMOS technology. This UWB transceiver can be employed for both radar sensing and communication purposes. The transceiver applies the On-Off Keying (OOK) modulation scheme to transmit short Gaussian pulse signals. The transmitter output power level is adjustable. The fully integrated UWB transceiver occupies a core area of 0.752mm^2 and the total die area of 1.274mm^2 with the pad ring inserted. The transceiver was simulated with overall power consumption of 40mW for radar sensing. The receiver is very sensitive to weak signals with a sensitivity of -73.01dBm. The average power of a single pulse is 9.8µW. The pulses are not posing any harm to human tissues. The sensing resolution and the target positioning precision are presumably sufficient for heart movement detection purpose in medical applications. This transceiver can also be used for high speed wireless data communications. The data transmission rate of 200 Mbps was achieved with an overall power consumption of 57mW. A combination of sensing and communications can be used to build a low power sensor

Design of an Ultra Low Power RFCMOS Transceiver for a Self-Powered IoT Node

In this thesis a transceiver characterized to consume ultra low power based in RFCMOS for a self-powered Internet of Things node is studied and designed. The transceiver consists in a simple Non-Coherent system, which means that the signal is picked up by the receiver based on energy detection, as a result it is one of the simplest existing transceivers once it does not need in the transmitter a complex pulse generator and certainly in the receiver as well. It is composed by an OOK modulator, a pulse generator that will determine the centre frequency and a driver amplifier connected to a 50W antenna for the transmitter. While in the receiver there is as first block a Low Noise Amplifier, a self-mixer that will prepare the signal for the integrator and a comparator working as a energy detector. The UWB transceiver will be able to operate with a centre frequency of 4.5 GHz and a bandwidth of at least 500 MHz. It is critical to notice that the system is consuming a value of 96 mW for the power and accomplishing the power spectrum density -43 dBm/MHz using an OOK modulation technique. The entire system was implemented with standard 130nm CMOS technology

Analog IC Design at the University of Twente

This article describes some recent research results from the IC Design group of the University of Twente, located in Enschede, The Netherlands.\ud \ud Our research focuses on analog CMOS circuit design with emphasis on high frequency and broadband circuits. With the trend of system integration in mind, we try to develop new circuit techniques that enable the next steps in system integration in nanometer CMOS technology. Our research funding comes from industry, as well as from governmental organizations. We aim to find fundamental solutions for practical problems of integrated circuits realized in industrial Silicon technologies.\ud \ud CMOS IC technology is dictated by optimal cost and performance of digital circuits and is certainly not optimized for nice analog behavior. As analog designers, we do not have the illusion to be able to change the CMOS technology, so we have to "live with it" and solve the problems by design. In this article several examples will be shown, where problematic analog behavior, such as noise and distortion, can be tackled with new circuit design techniques. These circuit techniques are developed in such a way that they do benefit from the modern technology and thus enable further integration. This way we can improve various analog building blocks for wireless, wire-line and optical communication. Below some examples are given.\ud \u