Correcting Charge-Constrained Errors in the Rank-Modulation Scheme

We investigate error-correcting codes for a the rank-modulation scheme with an application to flash memory devices. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, overcomes overshoot errors when programming cells (a serious problem that reduces the writing speed), and mitigates the problem of asymmetric errors. In this paper, we study the properties of error-correcting codes for charge-constrained errors in the rank-modulation scheme. In this error model the number of errors corresponds to the minimal number of adjacent transpositions required to change a given stored permutation to another erroneous one—a distance measure known as Kendall’s τ-distance.We show bounds on the size of such codes, and use metric-embedding techniques to give constructions which translate a wealth of knowledge of codes in the Lee metric to codes over permutations in Kendall’s τ-metric. Specifically, the one-error-correcting codes we construct are at least half the ball-packing upper bound

Interference Exploitation-based Hybrid Precoding with Robustness Against Phase Errors

Hybrid analog-digital precoding significantly reduces the hardware costs in massive MIMO transceivers when compared to fully-digital precoding at the expense of increased transmit power. In order to mitigate the above shortfall, we use the concept of constructive interference-based precoding, which has been shown to offer significant transmit power savings when compared with the conventional interference suppression-based precoding in fully-digital multiuser MIMO systems. Moreover, in order to circumvent the potential quality-of-service degradation at the users due to the hardware impairments in the transmitters, we judiciously incorporate robustness against such vulnerabilities in the precoder design. Since the undertaken constructive interference-based robust hybrid precoding problem is nonconvex with infinite constraints and thus difficult to solve optimally, we decompose the problem into two subtasks, namely, analog precoding and digital precoding. In this paper, we propose an algorithm to compute the optimal constructive interference-based robust digital precoders. Furthermore, we devise a scheme to facilitate the implementation of the proposed algorithm in a low-complexity and distributed manner. We also discuss block-level analog precoding techniques. Simulation results demonstrate the superiority of the proposed algorithm and its implementation scheme over the state-of-the-art methods

Constructions of Snake-in-the-Box Codes for Rank Modulation

Snake-in-the-box code is a Gray code which is capable of detecting a single error. Gray codes are important in the context of the rank modulation scheme which was suggested recently for representing information in flash memories. For a Gray code in this scheme the codewords are permutations, two consecutive codewords are obtained by using the "push-to-the-top" operation, and the distance measure is defined on permutations. In this paper the Kendall's $\tau$-metric is used as the distance measure. We present a general method for constructing such Gray codes. We apply the method recursively to obtain a snake of length $M_{2n+1}=((2n+1)(2n)-1)M_{2n-1}$ for permutations of $S_{2n+1}$, from a snake of length $M_{2n-1}$ for permutations of~$S_{2n-1}$. Thus, we have $\lim\limits_{n\to \infty} \frac{M_{2n+1}}{S_{2n+1}}\approx 0.4338$, improving on the previous known ratio of $\lim\limits_{n\to \infty} \frac{1}{\sqrt{\pi n}}$. By using the general method we also present a direct construction. This direct construction is based on necklaces and it might yield snakes of length $\frac{(2n+1)!}{2} -2n+1$ for permutations of $S_{2n+1}$. The direct construction was applied successfully for $S_7$ and $S_9$, and hence $\lim\limits_{n\to \infty} \frac{M_{2n+1}}{S_{2n+1}}\approx 0.4743$.Comment: IEEE Transactions on Information Theor

Trade-offs between Instantaneous and Total Capacity in Multi-Cell Flash Memories

The limited endurance of flash memories is a major design concern for enterprise storage systems. We propose a method to increase it by using relative (as opposed to fixed) cell levels and by representing the information with Write Asymmetric Memory (WAM) codes. Overall, our new method enables faster writes, improved reliability as well as improved endurance by allowing multiple writes between block erasures. We study the capacity of the new WAM codes with relative levels, where the information is represented by multiset permutations induced by the charge levels, and show that it achieves the capacity of any other WAM codes with the same number of writes. Specifically, we prove that it has the potential to double the total capacity of the memory. Since capacity can be achieved only with cells that have a large number of levels, we propose a new architecture that consists of multi-cells - each an aggregation of a number of floating gate transistors