Unordered Error-Correcting Codes and their Applications

We give efficient constructions for error correcting unordered {ECU) codes, i.e., codes such that any pair of codewords are at a certain minimal distance apart and at the same time they are unordered. These codes are used for detecting a predetermined number of (symmetric) errors and for detecting all unidirectional errors. We also give an application in parallel asynchronous communications

A Computational Framework for Efficient Error Correcting Codes Using an Artificial Neural Network Paradigm.

The quest for an efficient computational approach to neural connectivity problems has undergone a significant evolution in the last few years. The current best systems are far from equaling human performance, especially when a program of instructions is executed sequentially as in a von Neuman computer. On the other hand, neural net models are potential candidates for parallel processing since they explore many competing hypotheses simultaneously using massively parallel nets composed of many computational elements connected by links with variable weights. Thus, the application of modeling of a neural network must be complemented by deep insight into how to embed algorithms for an error correcting paradigm in order to gain the advantage of parallel computation. In this dissertation, we construct a neural network for single error detection and correction in linear codes. Then we present an error-detecting paradigm in the framework of neural networks. We consider the problem of error detection of systematic unidirectional codes which is assumed to have double or triple errors. The generalization of network construction for the error-detecting codes is discussed with a heuristic algorithm. We also describe models of the code construction, detection and correction of t-EC/d-ED/AUED (t-Error Correcting/d-Error Detecting/All Unidirectional Error Detecting) codes which are more general codes in the error correcting paradigm

Physical Optimization of Quantum Error Correction Circuits

Quantum error correcting codes have been developed to protect a quantum computer from decoherence due to a noisy environment. In this paper, we present two methods for optimizing the physical implementation of such error correction schemes. First, we discuss an optimal quantum circuit implementation of the smallest error-correcting code (the three bit code). Quantum circuits are physically implemented by serial pulses, i.e. by switching on and off external parameters in the Hamiltonian one after another. In contrast to this, we introduce a new parallel switching method that allows faster gate operation by switching all external parameters simultaneously. These two methods are applied to electron spins in coupled quantum dots subject to a Heisenberg coupling H=J(t) S_1*S_2 which can generate the universal quantum gate `square-root-of-swap'. Using parallel pulses, the encoding for three-bit quantum error correction in a Heisenberg system can be accelerated by a factor of about two. We point out that parallel switching has potential applications for arbitrary quantum computer architectures.Comment: 13 pages, 6 figure

Parallel Nonbinary LDPC Decoding on GPU

Nonbinary Low-Density Parity-Check (LDPC) codes are a class of error-correcting codes constructed over the Galois field GF(q) for q > 2. As extensions of binary LDPC codes, nonbinary LDPC codes can provide better error-correcting performance when the code length is short or moderate, but at a cost of higher decoding complexity. This paper proposes a massively parallel implementation of a nonbinary LDPC decoding accelerator based on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The implementation maps the Min-Max decoding algorithm to GPU’s massively parallel architecture. We highlight the methodology to partition the decoding task to a heterogeneous platform consisting of the CPU and GPU. The experimental results show that our GPUbased implementation can achieve high throughput while still providing great flexibility and scalability.National Science Foundation (NSF

Advanced channel coding for space mission telecommand links

We investigate and compare different options for updating the error correcting code currently used in space mission telecommand links. Taking as a reference the solutions recently emerged as the most promising ones, based on Low-Density Parity-Check codes, we explore the behavior of alternative schemes, based on parallel concatenated turbo codes and soft-decision decoded BCH codes. Our analysis shows that these further options can offer similar or even better performance.Comment: 5 pages, 7 figures, presented at IEEE VTC 2013 Fall, Las Vegas, USA, Sep. 2013 Proc. IEEE Vehicular Technology Conference (VTC 2013 Fall), ISBN 978-1-6185-9, Las Vegas, USA, Sep. 201

PERFORMANCE COMPARISON OF NEW DESIGNS OF CHIEN SEARCH AND SYNDROME BLOCKS FOR BCH AND REED SOLOMON CODES

Error correcting codes constitute one of the core technologies in telecommunications field, especially digital communication applications. The objective of this paper is to compare performance among new designs of chien search block on the one hand and syndrome architectures on the other hand in error correcting codes. All comparison of all designs is made by computing the number of logic, bit error rate values and number of iteration in the case of syndrome architectures Analysis results show that the performances of the new designs based on both second factorization method and Three-Parallel Syndrome architecture are superior to the performances of traditional designs

Construction of m-Repeated Burst Error Detecting and Correcting Non-binary Linear Codes

Error correcting codes are required to ensure reliable communication of digitally encoded information. One of the areas of practical importance in which a parallel growth of the subject error correcting codes took place is that of burst error detecting and correcting codes. The nature of burst errors differs from channel to channel depending upon the behavior of channels or the kind of errors which occur during the process of transmission. The rate of transmission is efficient if the number of parity-check digits are as minimum as possible. It is usually not possible to give the exact number of parity-check digits required for a given code. However, bounds can be obtained over the number of parity-check digits. An upper bound for a linear code capable of detecting/ correcting burst errors or its variants is many a times established by the technique used to establish Varsharmov-Gilbert-Sacks bound by constructing a parity-check matrix for the requisite code. This technique not only ensures the existence of such a code but also gives a method for constructing such a code. The synthesis method using this technique is cumbersome and to the best of our knowledge, there is no systematic way to construct a parity-check matrix for a burst error correcting non-binary linear code. Extending the algorithm for binary linear codes given by the authors to non-binary codes, the paper proposes a new algorithm for constructing a parity-check matrix for any linear code over GF(q) capable of detecting and correcting a new kind of burst error called `m-repeated burst error of length b or less\u27. Codes based on the proposed algorithm have been illustrated

Check-hybrid GLDPC Codes: Systematic Elimination of Trapping Sets and Guaranteed Error Correction Capability

In this paper, we propose a new approach to construct a class of check-hybrid generalized low-density parity-check (CH-GLDPC) codes which are free of small trapping sets. The approach is based on converting some selected check nodes involving a trapping set into super checks corresponding to a 2-error correcting component code. Specifically, we follow two main purposes to construct the check-hybrid codes; first, based on the knowledge of the trapping sets of the global LDPC code, single parity checks are replaced by super checks to disable the trapping sets. We show that by converting specified single check nodes, denoted as critical checks, to super checks in a trapping set, the parallel bit flipping (PBF) decoder corrects the errors on a trapping set and hence eliminates the trapping set. The second purpose is to minimize the rate loss caused by replacing the super checks through finding the minimum number of such critical checks. We also present an algorithm to find critical checks in a trapping set of column-weight 3 LDPC code and then provide upper bounds on the minimum number of such critical checks such that the decoder corrects all error patterns on elementary trapping sets. Moreover, we provide a fixed set for a class of constructed check-hybrid codes. The guaranteed error correction capability of the CH-GLDPC codes is also studied. We show that a CH-GLDPC code in which each variable node is connected to 2 super checks corresponding to a 2-error correcting component code corrects up to 5 errors. The results are also extended to column-weight 4 LDPC codes. Finally, we investigate the eliminating of trapping sets of a column-weight 3 LDPC code using the Gallager B decoding algorithm and generalize the results obtained for the PBF for the Gallager B decoding algorithm