A Survey of Techniques for Architecting TLBs

“Translation lookaside buffer” (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects and system engineers

멀티코어 시뮬레이터에서의 자동차 시스템을 위한 기능적/시간적 정확성 보장 시뮬레이션 기법

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 컴퓨터공학부, 2019. 2. 이창건.This dissertation presents functionally and temporally correct simulation method for cyber-side of an automotive system on multicore simulator. To overcome the limitations of the existing simulation methods which do not correctly model temporal behaviours such as varying execution times and task preemptions, the novel simulation technique assuming single core simulator was proposed. In this work, we extend the single core simulator to the multicore while keeping all of the proposed key ideas to guarantee correct simulation. We introduce heuristic task partitioning algorithm based on memory usages and approximated task-wise blockings of simulated tasks. As a result, we could improve up to 97%p, 15%p of simulation capacity compared to the single core, and other task partitioning algorithms, respectively.본 논문에서는 멀티 코어 시뮬레이터를 활용하여 자동차 사이버-물리 시스템의 사이버 시스템을 기능적/시간적으로 정확하게 시뮬레이션하기 위한 방법을 제시한다. 앞선 연구에서는 시스템의 기능적 행태뿐만 아니라 태스크의 가변 수행 시간, 자원 선점 등과 같은 시간적 행태 역시 함께 정확히 모사하기 위한 새로운 시뮬레이션 기법들이 제안되었다. 앞선 연구에서 제안된 시뮬레이션 기법들이 싱글코어 시뮬레이터만을 가정하고 있다는 점에 착안하여 본 논문에서는 정확한 시뮬레이션을 보장하기 위해 제안되었던 기존 연구의 주요 아이디어를 모두 유지하면서 싱글코어 시뮬레이터를 멀티코어 시뮬레이터로 확장한다. 제안하는 방법에서는 각 태스크의 메모리 사용량과 근사화 된 태스크 간 블로킹 값을 기반으로 시뮬레이션 대상 태스크에 대한 휴리스틱 태스크 분할 알고리즘을 설계한다. 또한, 임의적으로 생성한 다수의 워크로드를 사용하여 시뮬레이션 성능을 측정하고, 이를 통해 제안하는 방법이 싱글코어 시뮬레이터 및 다른 태스크 분할 알고리즘에 비해 각각 최대 97%p, 15%p의 향상된 시뮬레이션 용량을 갖는 것을 보인다. 결과적으로 제안하는 멀티코어 시뮬레이터는 앞선 연구에서 제안되었던 기능적/시간적 정확성을 동일하게 보장함과 동시에 보다 높은 시뮬레이션 용량을 제공함으로써 전체 자동차 시스템의 시뮬레이션에 효과적으로 활용될 수 있다.1 Introduction 1 1.1 Motivation and Objective 1 1.2 Approach 1 1.3 Organization 2 2 Related Work 3 2.1 Model-Based Simulations 3 2.2 Real-time Execution Platforms 3 2.3 Functionally and Temporally Correct Simulations 3 3 Background 5 3.1 Description on the real cyber-system 5 3.2 Description on the simulated cyber-system 7 3.3 Idea of Functionally and Temporally Correct Simulation 9 4 Problem Description 12 4.1 Keeping the key ideas of the single core simulator 12 4.2 Maximally utilizing the multicore 13 5 Proposed Approach 15 5.1 Memory constraint 15 5.2 The Smallest-blocking-first heuristic 18 5.2.1 Intuition of Smallest-blocking-first algorithm 19 5.2.2 Finding the Expected Earliest Start Time 20 5.2.3 Finding the Expected Latest Finish Time 22 5.2.4 Weighting the [EEST, ELFT] intervals 25 6 Evaluation 28 6.1 Simulatability according to the number of cores 28 6.2 Simulatability according to the partitioning method 30 6.3 Simulatability according to the physical read/write task ratio 31 7 Conclusion 35 References 37Maste

Dynamic Energy and Thermal Management of Multi-Core Mobile Platforms: A Survey

Multi-core mobile platforms are on rise as they enable efficient parallel processing to meet ever-increasing performance requirements. However, since these platforms need to cater for increasingly dynamic workloads, efficient dynamic resource management is desired mainly to enhance the energy and thermal efficiency for better user experience with increased operational time and lifetime of mobile devices. This article provides a survey of dynamic energy and thermal management approaches for multi-core mobile platforms. These approaches do either proactive or reactive management. The upcoming trends and open challenges are also discussed

High-Performance and Time-Predictable Embedded Computing

Nowadays, the prevalence of computing systems in our lives is so ubiquitous that we live in a cyber-physical world dominated by computer systems, from pacemakers to cars and airplanes. These systems demand for more computational performance to process large amounts of data from multiple data sources with guaranteed processing times. Actuating outside of the required timing bounds may cause the failure of the system, being vital for systems like planes, cars, business monitoring, e-trading, etc. High-Performance and Time-Predictable Embedded Computing presents recent advances in software architecture and tools to support such complex systems, enabling the design of embedded computing devices which are able to deliver high-performance whilst guaranteeing the application required timing bounds. Technical topics discussed in the book include: Parallel embedded platforms Programming models Mapping and scheduling of parallel computations Timing and schedulability analysis Runtimes and operating systems The work reflected in this book was done in the scope of the European project P SOCRATES, funded under the FP7 framework program of the European Commission. High-performance and time-predictable embedded computing is ideal for personnel in computer/communication/embedded industries as well as academic staff and master/research students in computer science, embedded systems, cyber-physical systems and internet-of-things.info:eu-repo/semantics/publishedVersio